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The name of the invention 参 channel stereo playback device
BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic diagram showing an example of a
quartic rough onit stereo device according to the invention comprising a company encoder and
decoder, and FIG. Jw J appears at m output terminals of the decoder of FIG. Fig. 3 is a chart
showing the thickness and phase of the output signal as a function of the azimuth angle
supplying the original signal to the encoder; Fig. 3 is a circuit diagram showing an example of the
connection arrangement of logic circuits according to the present invention; FIG. 3 is a waveform
diagram for explaining the operation of the circuit of FIG. 3, FIG. S is a circuit diagram showing
another example of the logic circuit according to the present invention, and 4m is a signal
appearing at various points in the circuit of FIG. Fig. 7 is a waveform diagram for explaining the
operation of the circuit of Fig. 5, Fig. 7 is a control of the logic circuit of the diagram j, showing
the magnitude and phase as a function of the azimuth angle at which the original signal is
supplied to the encoder. Characteristic diagram showing functions, EndPage: 17; 9 is FIG. FIG. 4
is a characteristic diagram showing the amplitude of the control signal generated by the logic
circuit of FIG. 3 as a function of the azimuth angle at which the original signal is supplied to the
encoder. / 17, / 2, / / #, / 6 ...: L, *-input terminal of x, x. n: output terminal of encoder, ll:
encoder, 195: horizontal rotation type voltage divider, l: control arm, 3. Jj (7 ° j j 2 入 力
decoder input terminal, I デ コ ー ダ decoder, 317 32 32 評, p j, R j, L, /, B, F デ コ ー ダ decoder
output terminal, n, 2s: Channel (recording medium), X. $117. U, 鐸, ko j da, n n ... vector
group (signal component klll! 0, jJ, jl, 14, JIO, J7J, Jul, Jj 4-gain control amplifier, rt, 40, 4! ... ・
・ ・: Control electrodes of the gain control amplifier, d4, 41, 717, 7 eL; # R'feL: aR:... Speaker, 7
reference, 74, 7? , 10 ... frequency response shaping network, 'I! r, 7? , 'It, II, Jj4 # l, 291, JOo,
302, Jll--amplifier, rJ, r #. rt, tt, de j, f? , RJ0, / JJ, II 亭, III. J * 1, Jj6: Rectifier, D /, 91, lJl, 129. III,
/ 亭 0, Jj4, 241, 291, JIO, #JJjul, 314 ′ ′-· · · · · addition and subtraction device, de J, 90, de $,
94.20 number circuit, rJ0, / JJ, / Jl, rJ4, 30II, 306. 3011, 310, J data λ, 3 data 6 ··· clip (limit)
amplifier, -II, 240, J j co, waste ··· phase shift network, 216 ··· logic and control circuit, 211, J de
0. Z de λ, Kotanote 5 ... addition / subtraction (mixing) device, 312, 3/6 ... addition device, 3
reference 波形 ... waveform shaping circuit, JIIl ... inverter, zst, ssr ... Slicer, L1: left front signal
component, 'Eta: right front signal component, Lb: left rear signal component, Rb: right rear
signal component, LT: first (left) synthesized signal , ... RT ... second, 2 (right IN) composite signal.
Patent Assignee Colimbia Broadcasting Systems Incorporated EndPage: 181 jjit?
Jiii5EndPage:19J7Ei、7175.! 5) List of attached documents [1) 1
statement (2) 1 drawing (3) request 1 copy (4) 1 letter of attorney (original and translated text)
(5) priority certificate 1 (original (Senior Time Corporation Certificate 1 (I) 7, Inventors other
than the above, patent applicants or agents (1) Inventors (2) Agent location Chiyoda-ku, Tokyo 32-4 Seki, Chiyoda-ku No. Zip Code 100 End Page: 21 Warning: Page Discontinuity