JPH06282279

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DESCRIPTION JPH06282279
[0001]
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is a noise
reduction device for reducing noise by adding antiphase noise to noise, such as noise in
passenger compartments such as passenger cars, buses, ships, aircrafts, cabins, etc. Can be
applied to the reduction of
[0002]
2. Description of the Related Art As a method of reducing noise by adding an antiphase sound to
noise, there is generally an adaptive control method as disclosed in Japanese Patent Laid-Open
No. 3-204354. Here, the signal from the crank angle sensor and the engine ignition pulse are
multiplied as they are and waveform-shaped. The waveform-shaped signal is processed in an
adaptive digital filter (Adaptive Digital Filter) and sent to a speaker. The sound emitted from the
speaker interferes with the noise from the engine, so the engine sound is silenced. In addition, a
microphone for error detection is placed at the periphery of the ear as residual sound detection
means, and the constant of the adaptive digital filter is corrected based on the signal detected by
the microphone.
[0003]
U.S. Pat. No. 4,977,600 discloses a noise reduction system technology in which speakers are
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provided on both upper sides of a vehicle seat, and a microphone for error detection is disposed
in proximity to the speakers. The microphone is guided from the back of the seat to the ear by
telescopic support.
[0004]
SUMMARY OF THE INVENTION In the above-mentioned technology, if the error detection
microphone is extended from the sheet to the ear, movement of the head is impeded. For
example, when you move your head suddenly, such as looking back suddenly, you hit your head
against the microphone. Therefore, I want to fix the microphone near the seat or the speaker, but
the microphone gets away from the ear, and the muffling effect becomes indeterminate.
[0005]
Therefore, in the present invention, it is an object to obtain sufficient muffling efficiency without
extending the microphone to the ear.
[0006]
In order to solve the above-mentioned problems, the first means used in the invention of claim 1
adaptively controls the noise detection means for detecting noise and the detection output of the
noise detection means. In a noise reduction device including an adaptive digital filter, a speaker
generating sound indoors based on an output signal of the adaptive digital filter, and an error
detection microphone detecting an indoor sound and feeding it back to the adaptive digital filter,
the speaker cone is a speaker cone And the bass reflex hole, and the error detection microphone
is installed on the middle line between the speaker cone of the speaker and the bass reflex hole.
[0007]
In order to solve the above problems, a second means used in the invention of claim 2 is that, in
addition to the first means, an error detection microphone is provided on the side of the speaker.
[0008]
According to the first means, the adaptive digital filter produces antiphase sound of noise and
makes it sound from the speaker.
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As a result, the noise is canceled by the antiphase sound and the muffling is performed.
If the muffling is not sufficient, a sound not muffled by the error detection microphone is
detected and fed back to the adaptive digital filter.
As a result, feedback control is performed so that the sound detected by the error detection
microphone is minimized, and noise is efficiently silenced. Here, since the error detection
microphone is placed on the middle line between the speaker cone of the speaker and the bass
reflex hole, muffling is reliably performed in a wide range near the identity.
[0009]
The muffling becomes effective as the headrest surface is approached.
[0010]
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT An embodiment of the present
invention mounted on a vehicle will now be described with reference to the drawings.
FIG. 1 is an overall schematic view of the present invention. The speaker SP and the error
detection microphone M extend from the headrest 11 of the seat 10 to the ear. The speaker SP
and the error detection microphone M may extend from the backrest 14 of the seat 10. The
engine 12 operates in response to the ignition pulse signal E. The pulse conversion circuit PTC
receives the ignition pulse signal E of the engine 12 and outputs a pulse signal ET. The pulse
signal ET has the same frequency as the ignition pulse signal E, and is a pulse signal having a
duty of 50%. The pulse signal ET is input to a waveform shaping circuit WFC and a phased lock
loop PLL. The waveform shaping circuit WFC receives the pulse signal ET, and outputs a
reference signal PA obtained by shaping the pulse signal ET. The phase locked loop PLL
generates a clock pulse CL. The clock pulse CL is a pulse signal having a frequency that is a
predetermined multiple of the pulse signal ET. Clock pulse CL is applied to frequency selector
SCF. The frequency selector SCF receives the error signal VB from the error detection
microphone M and outputs an error signal PD. The frequency selector SCF works to pass only the
frequency band determined by the clock pulse CL. An adaptive digital filter (Adaptive Digital
Filter) ADF, which is an adaptive filter, receives the reference signal PA and the error signal PD,
and outputs a mute signal PB. The adaptive digital filter ADF adjusts the phase and gain of the
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reference signal PA so as to minimize the error signal PD, which is a feedback signal, and outputs
the adjusted signal as the mute signal PB. The mute signal is output as sound at the speaker SP.
[0011]
Here, the configuration of the pulse conversion circuit PTC will be described with reference to
FIG. The external clock output of the external clock generation circuit 20 for generating an
external clock of 10 KHz is connected to the clock terminal of the binary counter 21 and the
clock down terminal of the up / down counter 24. Here, SPG8640B is used as the external clock
generation circuit 20. In addition, the dual 4-bit 74HC 393 is used for the binary counter 21 and
the 74HC193 is used for the up / down counter 24. The ignition pulse signal E is input to a short
pulse conversion circuit 23 configured of a NOT gate, a resistor, a capacitor, and a NAND gate.
The load signal which is the output of the short pulse signal conversion circuit 23 is further
inverted, delayed by the delay circuit 22, and then sent to the binary counter 21 as a reset signal.
Here, the delay circuit 22 uses DCE 35-20. The second to eighth bits (Q2 to 8) of the output of
the binary counter 21 are the first to seventh bits of the input of the up / down counter 24 or 25
(P0 to P3 of the up / down counter 24, P0 to 2 of the up / down counter 25) It is connected to
the. The outputs of the up / down counters 24 and 25 (Q 0 to 3 of the up / down counter 24 and
Q 0 to 2 of the up / down counter 25) are inverted by the NOT gate and input to the NAND gate
26. The load signal and the output of the NAND gate 26 are inverted by the NOT gate and input
to the OR gate 27. The output of the OR gate 27 is input to the clock terminal of the JK flip flop
28.
[0012]
Next, the operation of the pulse conversion circuit PTC will be described with reference to FIG.
First, an external clock generation circuit 20 generates an external clock of 10 KHz. The external
clock is used as a clock for the binary counter 21 and the up / down counter 24. The short pulse
conversion circuit 23 converts an input ignition pulse signal E into a load signal. Here, the
ignition pulse signal E is inverted, delayed by a delay circuit using a resistor and a capacitor, and
the delayed signal and the ignition pulse signal are ANDed. As a result, the output of the short
pulse conversion circuit 23 becomes low only for a predetermined time determined by the
resistor and the capacitor from the rise of the ignition pulse signal E. The load signal which is the
output of the short pulse signal conversion circuit 23 is further inverted, delayed by the delay
circuit 22, and then sent to the binary counter 21 as a reset signal.
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[0013]
The binary counter 21 is reset by the reset signal and counts up at the rising edge of the external
clock. The load signal is input to the up / down counters 24 and 25 at the rise of the ignition
pulse, and the value of the input at that time is set.
[0014]
After that, it counts down every time the external clock comes. The binary counter 21 is reset
after the up / down counters 24 and 25 set the input value under the influence of the delay
circuit 22 and starts counting up again. The second to eighth bits (Q2 to 8) of the output of the
binary counter 21 are the first to seventh bits of the input of the up / down counter 24 or 25 (P0
to P3 of the up / down counter 24, P0 to 2 of the up / down counter 25) At the time of loading,
half of the count value of the binary counter 21 is set. In this way, in half the cycle of the ignition
pulse, the count value becomes zero, and a state appears in which the load signal, the outputs Q0
to 3 of the up / down counter 24 and the outputs Q0 to 2 of the up / down counter 25 all
become low. . When the outputs of the up / down counters 24 and 25 are respectively inverted
and input to the NAND gate 26, a low level output can be obtained from the NAND gate 26 when
all the outputs of the up / down counters 24 and 25 are low. When the load signal and the
output of the NAND gate 26 are respectively inverted and input to the OR gate 27, the output of
the OR gate 27 generates a short pulse which becomes high level every half cycle of the ignition
pulse. When the output of the OR gate 27 is input to the clock terminal of the J-K flip flop 28, a
high level signal of the OR gate 27 can be used as a trigger to output a pulse signal ET having a
duty of 50%.
[0015]
The internal structure of the phase locked loop PLL is shown in FIG. The phase-locked loop PLL
includes a phase comparator 31, a loop filter 32, a voltage control oscillator 33, and a divider.
The phase comparator 31 outputs a phase error between the duty converted ignition pulse signal
ET and the output of the frequency divider 34 to the loop filter 32 as a signal. The loop filter 22
takes the form of an integrator and delivers the phase error signal in the form of an analog
voltage to the voltage controlled oscillator 33. The voltage control oscillator 33 oscillates a
frequency pulse corresponding to the input voltage and outputs it as a clock pulse CL and sends
it to the phase comparator 31. The clock pulse CL is set to be N times the frequency of the
ignition pulse signal ET. The value of N is set in advance. The divider 34 divides the clock pulse
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CL and outputs a divided signal to the phase comparator 31. The frequency divider 34 is set to
set the frequency of the clock pulse CL to 1 / N.
[0016]
Now, it is assumed that N times the frequency of the ignition pulse signal E matches the
frequency of the clock pulse CL. Here, when the engine speed increases, a phase difference
occurs between the pulse from the frequency divider 23 and the ignition pulse signal ET. At this
time, the phase comparator 31 outputs a signal corresponding to this phase difference. When the
phase increases, the output pulse voltage is increased, and when the phase difference decreases,
the output pulse voltage is decreased. The loop filter 32 converts the output pulse into an analog
voltage, and the voltage control oscillator 33 generates a clock pulse of a frequency
corresponding to this analog voltage. Thus, when the phase difference increases, the clock
frequency increases, and when the phase difference decreases, the clock frequency decreases.
Therefore, the clock frequency goes up and down according to the engine speed. Since the loop
filter 32 has an integrator configuration, the phase difference matches, and even if the pulse
from the charge pump is not output, the previous value is continuously output. Therefore, the
frequency of the clock pulse CL is N times the engine speed.
[0017]
The frequency selector SCF is a switched capacitor filter. The switched capacitor filter is an
integrator to which the property of a switched capacitor having an equivalent resistance Req of 1
/ (C · fc) is applied. When designing a filter, if this Req is a resistor, a filter that follows changes in
fc can be realized. As a switched capacitor filter, there is an MF10 universal monolithic dual
switched capacitor filter manufactured by National Semiconductor. By using this MF 10, it is
possible to form a band pass filter that extracts only the frequency band corresponding to the
frequency fc of the clock pulse CK.
[0018]
A clock pulse having a frequency N times the frequency of the engine speed is applied to the
frequency selector SCF, and the frequency selector SCF adjusts the frequency band to be selected
according to the frequency of the clock pulse CL. By adjusting this value N and the voltage range
of the voltage control oscillator 33, it is possible to obtain a band pass filter that can extract only
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a frequency that is a predetermined multiple of the engine speed. Thereby, only the n-th
harmonic component of the engine speed can be extracted from the sound detected by the error
detection microphone M. Normally, in a 4-cylinder engine, the level of the second harmonic
component of the engine speed is high, and this is a factor of noise in the passenger
compartment. Therefore, in the case of a 4-cylinder car, the value N and the voltage of the
voltage control oscillator 33 It is good to adjust the range and sort the frequency per twice the
engine speed.
[0019]
Here, a pulse wave ET having a duty of 50% having the same frequency as the frequency of the
ignition pulse signal E of the engine is sent to the phase-locked loop PLL by the pulse conversion
circuit PTC. As shown in FIG. 5, when the duty of the input signal of the phase comparator 31 of
the phase-locked loop PLL is 50%, the phase difference between the signal input to the phase
comparator 31 and the output signal of the voltage control oscillator 33 is simple. The voltage
control oscillator 33 simply operates to reduce this phase difference. However, as shown in FIG.
6, if the duty of the input signal of the phase comparator 31 is not 50%, the phase difference
between the signal input to the phase comparator 31 and the output signal of the voltage control
oscillator 33 is not simple. The operation of the oscillator 33 is complicated, and the voltage
commensurate with the phase difference is also disturbed by increase or decrease. As a result,
the oscillation frequency of the voltage control oscillator 33 also fluctuates sharply. When the
frequency selector SCF receives this pulse with a large fluctuation as a clock pulse, it can not pass
the desired frequency. Therefore, the duty of the output pulse of the pulse conversion circuit PTC
is desirably 50%. In the present embodiment, the pulse conversion circuit PTC generates a pulse
wave ET of 50% duty with the same frequency as the frequency of the ignition pulse signal E of
the engine, and is used as the input of the loop filter PLL. SCF operates stably.
[0020]
The sound produced by the speaker goes into the driver's and passenger's ears together with the
noise that comes from the engine and the outside of the vehicle interior. At the same time, these
sounds are detected by the error detection microphone M. The output VB of the error detection
microphone M is sent to the adaptive digital filter ADF. The adaptive digital filter ADF comprises
a transversal filter 35 and an adaptive algorithm 36, as shown in FIG. The adaptive algorithm 36
receives the output VB of the error detection microphone M and determines the filter coefficient
of the transversal filter 35. The transversal filter 35 shapes the ignition pulse of the engine,
convolutes the reference signal PA converted into the sound signal, and sends the signal sound
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PB to the speaker SP. Thereby, the adaptive digital filter ADF adjusts the filter coefficient so as to
minimize the level of the detection sound of the error detection microphone M.
[0021]
By inserting a band pass filter that follows only the frequency range of noise on the error
detection microphone M side, only noise can be muffled reliably.
[0022]
7 and 8 show the specific construction of the headrest portion of the seat.
A speaker SP is mounted to extend from the headrest 11 to both sides via a support member 17.
The support member 17 doubles as a speaker box. The speaker SP includes a speaker cone 15
and a bass reflex hole 16. The error detection microphone M is disposed on an intermediate line
between the speaker cone 15 and the bass reflex hole 16.
[0023]
A person places his head in front of the headrest 11. A person's ear is in front of the speaker
cone 15, usually at a position of about 0 to 5 cm from the front of the headrest 11. The speaker
SP is disposed to be inclined inward toward the human ear. In addition, the error detection
microphone M uses an omnidirectional one as much as possible. With such an arrangement, the
speaker SP can most effectively cancel noise with respect to the error detection microphone M,
and can mute the noise with the minimum necessary power. However, the error detection
microphone M can not be placed at the actual position of the ear. Further, since the power of the
speaker SP is small, the amount of muffling differs depending on the position of the error
detection microphone M. This is because the amount of muffling is inferior near the ear even
though muffling can be performed efficiently at the position of the error detection microphone
M. Therefore, the determination of the position of the error detection microphone M is
important.
[0024]
As shown in FIG. 9, the noise speaker 18 was disposed in front of the sheet 10, and the three
error detection microphones MA, MB, and MC were disposed at different positions to confirm the
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muffling amount.
[0025]
Here, a sound of 130 Hz was generated from the noise speaker 18 and the speaker SP.
The error detection microphones were arranged as shown in FIGS. The error detection
microphone MA was placed directly above the speaker cone 15. The error detection microphone
MB is disposed at a position between the speaker cone 15 and the bass reflex hole 16 and at a
position far from the ear. The error detection microphone MC is disposed at a position near the
ear at an intermediate position between the speaker cone 15 and the bass reflex hole 16. In the
figure, the x-axis indicates the forward direction of the sheet, the y-axis indicates the lateral
direction, and the z-axis indicates the upward direction. The origin of each axis is the center
position of the headrest 11 and the upper end of the speaker SP on the entire surface of the
headrest 11. The sound in each range of x = 0 to 15 cm, y = -20 to 20 cm, z = -15 to 0 cm was
measured, each separated by 5 cm. The measurement results are as shown in FIGS. Here, it is
described that the amount of muffling is superior as the density is darker. In addition, the area
where the volume is higher than the area where it can not be muted is the opposite.
[0026]
As a result, although there are many parts where the amount of muffling is high at the position A
of the error detection microphone MA, there are places where the muffling can not be performed
sufficiently. Although there is a lot of variation at the position B of the error detection
microphone MB, the noise has been reliably muffled in the measurement area. At position C of
the error detection microphone MC, muting was performed most stably among the positions.
[0027]
FIG. 15 is a graph showing the change in the x-axis direction at the positions of y = −10 cm and
z = −10 cm where the probability of having the position of the ear is high. The position of 0 to 5
cm in the x direction is the ear position. At position A of error detection microphone MA, the
amount of muffling becomes highest in the range of 5 to 10 cm, while at position B of error
detection microphone MB and position C of error detection microphone MC, the amount of
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muffling decreases as the distance increases. It turns out that it becomes. At the position A of the
error detection microphone MA, the muffling power is most needed and affects far. From this
result, it was found that the position B of the error detection microphone MB and the position C
of the error detection microphone MC are superior to the position A of the error detection
microphone MA in the muffling effect at the ear position. In addition, it was found that the
speaker SP emits canceling sound with appropriate power at the position B of the error detection
microphone MB rather than the position C of the error detection microphone MC, and the
muffling amount is improved.
[0028]
In the above embodiment, since control is performed by separating only the noise frequency
band, noise can be silenced surely and the convergence speed of the adaptive digital filter ADF is
improved. Therefore, the effectiveness of the adaptive digital filter ADF is increased.
[0029]
In the case of a six-cylinder engine, the rotational primary component, the 1.5th component, the
secondary component, the 2.5th component and the tertiary component of the engine appear in
the noise distribution in the vehicle compartment. When it is desired to mute all of these
components, a plurality of frequency multipliers are provided to multiply the signal obtained
from the ignition pulse of the engine, and the respective outputs are combined and input to the
adaptive digital filter ADF. A plurality of components may be provided, each component may be
extracted and then combined, and fed back to the adaptive digital filter ADF.
[0030]
In the above embodiment, noise is detected by the pulse conversion circuit PTC receiving the
ignition pulse of the engine and the waveform shaping circuit WFC as noise detection means.
However, a noise detection microphone is actually disposed, and the noise detection microphone
is used. The measured noise may be applied to the adaptive digital filter. In this case, in order to
make the adaptive digital filter work efficiently, a frequency tracking type band pass filter that
passes only the noise frequency (engine rotation frequency) or its multiplied frequency region
between the noise detection microphone and the adaptive digital filter ( A switched capacitor
filter may be arranged. In this case, only the noise is muted, and necessary sounds such as music,
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voice, alarm, warning sound and the like are not muted, so that it can be installed in a car.
[0031]
Although the apparatus for reducing engine noise in a vehicle is shown in the above embodiment,
the present invention is not limited to the engine, and can be applied to any apparatus in which
the frequency of the noise part changes according to the state of the noise source. For example,
there are a number of possible applications, such as reducing engine noise in an airplane room,
and reducing noise emitted from equipment such as a treatment placed on the side of the bed,
for use in a patient's bed in a hospital. In this case, the noise of an arbitrary frequency band may
be reduced by adjusting the clock of the switched capacitor filter. For vehicles, it is also effective
in reducing the operating noise of the seat adjuster and sliding noise of the wiper, the noise at
the time of shift change emitted by the transmission, and the operating noise of the solenoid
valve mounted on the vehicle.
[0032]
Since the speaker SP and the error detection microphone M2 are disposed near the human ear,
the speaker SP does not have to make a loud sound. For this reason, the sound emitted from the
speaker SP affects the part away from the seat 10 and the outside of the vehicle, and the sound is
not emphasized in other parts. Therefore, the noise only in the ear of the person sitting on the
seat is reduced and nothing else is affected.
[0033]
When the present invention is mounted on a vehicle, the noise reduction device of the present
invention can be mounted on each seat. In this case, it is preferable to provide a switch for
permitting / prohibiting the operation of the present apparatus so that each seat can be switched.
For example, the person who sleeps in the rear seat can operate this device, and the driver can
turn off the operation of this device to confirm the engine sound and prevent drowsiness, etc.
Becomes possible.
[0034]
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In the above embodiment, the pulse conversion circuit PTC and the waveform shaping circuit
WFC, which are noise detection means for detecting noise, the adaptive digital filter ADF for
receiving and controlling the detection output, and the output signal of the adaptive digital filter
ADF The speaker SP includes a speaker SP that generates sound and an error detection
microphone M that detects sound in the room and feeds it back to an adaptive digital filter, and
the speaker SP has a speaker cone 15 and a bass reflex hole 16 and the error detection
microphone M It is installed on the middle line (B and C positions) of the speaker cone of the
speaker and the bass reflex hole. Therefore, even if the error detection microphone is not
extended to the ear, the muffling effect at the ear position is excellent. Also, since the error
detection microphone is not extended to the ear, it does not get in the way.
[0035]
Further, in the above embodiment, since the error detection microphone M is further installed on
the side surface (position B) of the speaker, the noise in the vicinity of the head can be further
improved by 5 dB so that a more comfortable space can be obtained. become.
[0036]
According to the present invention of claim 1, the muffling effect at the ear position is excellent
without extending the error detection microphone to the ear.
Also, since the error detection microphone is not extended to the ear, it does not get in the way.
[0037]
According to the present invention of claim 2, the noise in the vicinity of the head can be further
improved by 5 dB, and a more comfortable space can be obtained.
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