JP2015506641

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DESCRIPTION JP2015506641
The present invention relates to a method of manufacturing a capacitive micromachined
transducer 100, in particular a CMUT. The method comprises the steps of: depositing a first
electrode layer 10 on a substrate 1; depositing a first dielectric film 20 on the first electrode
layer 10; Depositing a removable sacrificial layer 30 to form a transducer cavity 35 thereon;
depositing a second dielectric film 40 on the sacrificial layer 30; Depositing a second electrode
layer 50 thereon; and patterning at least one of the deposited layers and films 10, 20, 30, 40, 50.
The deposition step is performed by atomic layer deposition. The invention further relates to a
capacitive microfabricated transducer 100 manufactured by such a method, in particular a
CMUT.
Capacitive micromachined transducer and method of manufacturing the same
[0001]
The present invention relates to a capacitive microfabricated transducer, in particular to a
method of manufacturing a capacitive microfabricated ultrasonic transducer (CMUT) for
transmitting and / or receiving ultrasonic waves. The invention further relates to a capacitive
micromachined transducer, in particular a capacitive micromachined ultrasound transducer
(CMUT) for transmitting and / or receiving ultrasound.
[0002]
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The heart of any ultrasound (imaging) system is a transducer that converts electrical energy into
acoustic energy and acoustic energy into electrical energy. Traditionally, these transducers
consist of piezoelectric crystals operating at frequencies up to 10 MHz, arranged in a linear (1D)
transducer array. However, the trend towards matrix (2D) transducer arrays and the move
towards miniaturization to incorporate ultrasound (imaging) functionality into catheters and
guidewires is a so-called capacitive micromachined ultrasound transducer (CMUT: capacitive
micro) -developed and developed a -machined ultrasound transducer). The CMUT includes a thin
film (or diaphragm), a cavity under the thin film, and electrodes forming a capacitor. At the
reception of the ultrasound waves, the ultrasound waves cause the membrane to move or vibrate
and fluctuations in the capacitance between the electrodes can be detected. The ultrasound is
thereby converted into a corresponding electrical signal. On the contrary, when an electrical
signal is applied to the electrodes, the thin film moves or vibrates, whereby ultrasonic waves are
transmitted.
[0003]
However, charging is a well known drawback of capacitive micromachined ultrasound
transducers. WO 2010/032156 A2 discloses a capacitive micromachined ultrasound transducer
with a specific layer structure that solves the charging problem. A first insulating layer
comprising a dielectric is disposed between the first electrode and the second electrode. Also, a
second insulating layer comprising a dielectric can be disposed between the second electrode
and the cavity. In particular, so-called ONO (Oxide-Nitride-Oxide) dielectric layers provide a
solution to charging.
[0004]
In WO 2010/032156 A2, the first dielectric insulating layer and the second dielectric insulating
layer electrically insulate the first electrode and the second electrode. Such dielectric isolation
layer determines to a large extent the overall performance of the CMUT device. In the ideal case,
the dielectric insulating layer is very thin or has a high dielectric constant and a high breakdown
voltage. However, ONO dielectric layers are limited, and the dielectric constant of nitrogen is
about 5-7, so it can only be deposited with relatively thick (e.g., about 250 nm using PECVD)
layers and low dielectric constants. Thus, the performance of the CMUT is limited by the
minimum thickness of the ONO dielectric layer, the electrical breakdown voltage, and the
dielectric constant. A particular problem of such CMUT devices may be that the operating voltage
is relatively high and the output pressure is relatively low. Thus, there is a need to further
improve such CMUTs.
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[0005]
It is an object of the invention to provide an improved capacitive microfabricated transducer (in
particular a CMUT), in particular a capacity with improved performance (e.g. reduced operating
voltage and / or increased output pressure) and / or easier manufacture. It is an object of the
present invention to provide a mold microfabricated transducer. A further object of the present
invention is to provide an improved method of manufacturing such capacitive microfabricated
transducers, in particular CMUTs.
[0006]
In a first aspect of the invention, a method of manufacturing a capacitive micromachined
transducer, in particular a CMUT, is provided. The method comprises the steps of: depositing a
first electrode layer on a substrate; depositing a first dielectric film on the first electrode layer;
and depositing a sacrificial layer on the first dielectric film. Depositing the sacrificial layer is
removable to form a transducer cavity, depositing a second dielectric film over the sacrificial
layer, and depositing the second dielectric film. Depositing a second electrode layer thereon and
patterning at least one layer and / or film of the deposited layer and film, the deposition step
being performed by atomic layer deposition.
[0007]
In another aspect of the invention, there is provided a capacitive microfabricated transducer, in
particular a CMUT, manufactured by the method of the invention.
[0008]
In another aspect of the present invention, a first electrode layer on a substrate, a first dielectric
film on the first electrode layer, a cavity formed above the first dielectric film, and a cavity are
provided. Capacitive type including a covering second dielectric film and a second electrode layer
on the second dielectric film, wherein at least one layer and / or film of the deposited layer and
film is patterned A microfabricated transducer, in particular a CMUT, is provided.
[0009]
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The basic concept of the present invention is to use atomic layer deposition (ALD) in the
manufacturing method.
ALD technology offers the advantages and options to overcome current process limitations and
hence CMUT performance limitations.
All CMUT functional layers are deposited in a single process sequence, especially in a controlled
environment without exposing the substrate to the surrounding environment as was generally
required during prior art processing A method of manufacture is provided. The CMUT functional
layer is specifically a first electrode layer (providing a first electrode), a first dielectric film
(providing electrical insulation), a sacrificial layer (forming a cavity), (electrical insulation A
second dielectric film, and a second electrode film (a second electrode). This process is also
referred to as a full layer ALD (AL-ALD) CMUT process. In this way, a wafer with a stack of
deposited layers (or films) is realized. A very clean material interface can be achieved since the
wafer does not leave the ALD apparatus when growing the layer stack. Furthermore,
performance can be improved by controlling and fine-tuning, for example, the stress and charge
characteristics of the individual layers and interfaces.
[0010]
The manufacturing method uses in particular "top-bottom" patterning. Top-bottom patterning
provides a CMUT with a distinctive pyramidal structure, in particular a staircase pyramidal
structure. This typical cross-sectional view can be confirmed by an analysis method using, for
example, an FIB or SEM (scanning electron microscope) cross-sectional view. Patterning refers to
patterning a structure (eg, a stack of deposited layers). This may be performed, for example,
using (photo) lithography in which the photosensitive material is exposed. The exposure tool is
called a stepper. A photosensitive layer called a resist is developed. The pattern may be etched in
layers. The etching process may be a "wet" or "dry" process.
[0011]
Atomic layer deposition is a thin film deposition technique based on the continuous use of gas
phase chemical processing. Most of the ALD reactions use two chemicals, typically referred to as
"precursors". These precursors react continuously with the surface, one material at a time. A thin
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film is deposited by repeatedly exposing the precursor to the growth surface. ALD is a selflimiting (i.e., constant amount of thin film material deposited in each reaction cycle) continuous
surface chemical reaction that deposits a conformal thin film of material on a substrate of
different composition. ALD deposited layers are generally amorphous. ALD deposited layers are
generally high quality, pinhole free, and can be deposited at low temperatures. Due to the low
processing temperature, ALD is compatible with CMOS. Thin dielectric insulation layers result in
higher output pressure at lower operating voltages and improved reception sensitivity. This is
because the electric force between the electrodes draws the thin film in the direction toward the
bottom of the cavity. A thin dielectric film or material with high dielectric constant (also called
high epsilon material or high-k material) significantly increases this power and produces or
receives more output power (based on Coulomb's inverse square law) Increase sensitivity. This is
especially true for CMUTs operating in collapsed mode (ie, where the thin film partially touches
the bottom of the cavity during operation, eg by applying a bias voltage between the electrodes),
but generally It is also effective in CMUT in non-sinking mode.
[0012]
Preferred embodiments of the invention are defined in the dependent claims. It is to be
understood that the claimed CMUT has the same and / or identical preferred embodiments as the
claimed method and the embodiments recited in the dependent claims. Similarly, it should be
understood that the methods recited in the claims have similar and / or identical preferred
embodiments to the embodiments recited in the CMUTs and dependent claims.
[0013]
In a particularly preferred embodiment, the first dielectric film and / or the second dielectric film
comprises a first layer comprising an oxide, a second layer comprising a high-k material, and a
third comprising an oxide. Containing layers of Thus, the dielectric insulating layer comprises an
oxide layer (O), a high-k layer, and a further oxide layer (O). In other words, the high-k layer is
sandwiched between two oxide layers (especially silicone oxide). これは、いわゆるラミネートで
ある。 high-k refers to a high dielectric constant (e.g., 8 or more). The dielectric constant is
generally abbreviated by the letter k (or ε r). In this way, transducer performance can be
significantly improved (eg, higher output pressure at lower operating voltages) as compared to
the ONO dielectric insulation layer. Thus, replacing the ONO dielectric isolation layer with high-k
materials deposited by atomic layer deposition (ALD) significantly improves CMUT performance
with respect to operating voltage and output pressure. Furthermore, similar performance
(especially stable power versus time) can be achieved with respect to device stability as
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compared to ONO dielectric isolation layers. In other words, the laminate does not store charge
that causes the ultrasound output to drift.
[0014]
In a variant of this embodiment, the high-k material is aluminum oxide (Al 2 O 3) and / or
hafnium oxide (HfO 2). Aluminum oxide (k or ε r: 7-9, especially about 8 or 9) or hafnium oxide
(k or ε r: 12-27, especially about 14 or 20) has a high dielectric constant. In one example, an
(alternating layer) laminate of oxide-aluminum oxide-oxide (abbreviated OAO) may be provided
in this way. In another example, an (alternate layer) laminate of oxide-hafnium oxide-oxide
(abbreviated OHO) may be provided in this way.
[0015]
In another variation of this embodiment, the second layer includes a first sublayer comprising
aluminum oxide, a second sublayer comprising hafnium oxide, and a third sublayer comprising
aluminum oxide. In this way, an (alternate layer) laminate of oxide-aluminum oxide-hafnium
oxide-aluminum oxide-oxide (abbreviated OAHAO) can be provided. Aluminum oxide (also called
alumina) has a high dielectric constant and a high electrical breakdown voltage. Hafnium oxide
has a higher dielectric constant but lower breakdown voltage. Thus, the OAHAO dielectric
insulating layer combines low stress, high dielectric constant, and high breakdown voltage.
[0016]
In another variation, the thickness of the second layer is less than 100 nm. In this way,
particularly thin layers of ALD can be provided using very thin layers.
[0017]
In one embodiment, patterning comprises patterning the second electrode layer. By doing this,
the horizontal dimension of the second electrode can be determined. For example, the second
electrode layer may be patterned to be smaller than the first electrode layer. In this way, "topbottom" patterning is performed (e.g., using a first etch mask). Thus, a characteristic pyramid
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structure, in particular a step pyramid structure, is provided.
[0018]
In another embodiment or variant, the patterning comprises patterning the sacrificial layer and /
or the first electrode layer. By patterning the sacrificial layer, the horizontal dimension of the
cavity is defined. "Top-bottom" patterning is further performed in this manner (e.g., using a
second etch mask). The patterning of the sacrificial layer may be performed in a separate step
from the step of patterning the second electrode layer. Alternatively, the patterning of the
sacrificial layer and the patterning of the second electrode layer may be performed in a common
step. By patterning the first electrode layer, the horizontal dimension of the first electrode is
determined. "Top-bottom" patterning is further performed in this manner (e.g., using a third etch
mask). The patterning of the first electrode layer may be performed in a step separate from the
step of patterning the second electrode layer and / or the step of patterning the sacrificial layer.
Alternatively, the patterning of the first electrode layer and the patterning of the sacrificial layer
may be performed in a common step. Also, this may be performed in a step common to the
patterning of the second electrode layer.
[0019]
In other embodiments, most or all of the deposited layers and films are patterned. Specifically,
most or all of the layers and films deposited by ALD are patterned after ALD deposition.
Specifically, all CMUT functional layers are patterned. More specifically, the first electrode layer,
the first dielectric film, the sacrificial layer, the second dielectric film, and the second electrode
layer are patterned. The patterning may include multiple steps, for example, a first step of
patterning the top layer (s) and a second step of patterning the bottom layer (s). In each step, the
layer may be patterned to have different horizontal dimensions (in a direction parallel to the top
surface of the layer). In this way, a (step) pyramid structure can be created. Alternatively, the
patterning may be performed in a single step where the layers are patterned to have the same
horizontal dimension.
[0020]
In another embodiment, the method further comprises depositing a deposited layer and a
dielectric layer covering the film. This deposition step can in particular be carried out using
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atomic layer deposition. The dielectric layer may in particular cover the top and sides of the
deposited layer and the film with substantially the same coverage. This provides a very good step
coverage, in particular by atomic layer deposition.
[0021]
In another embodiment, the method further comprises removing the sacrificial layer by providing
an etch hole to etch the sacrificial layer to form a cavity. By doing this, the cavity of the CMUT
can be easily provided (for example, using the fourth etching mask).
[0022]
In another embodiment, the first electrode layer and / or the second electrode layer comprises a
non-metallic conductive material. In this way, atomic layer deposition techniques can provide the
unique option of depositing all the functional layers of the CMUT in a single process sequence.
The non-metallic conductive material may be, for example, a semiconductor.
[0023]
In a variation of this embodiment, the non-metallic conductive material is TiN (titanium nitride),
TaN (tantalum nitride), TaCN, IrO 2 (iridium oxide), ITO (indium tin oxide), LaNiO 3, and SrRuO 3
(ruthenium Acid) and at least one material selected from the group comprising These materials
are suitable for atomic layer deposition. In a variant of this variant, the non-metallic conductive
material is TiN (titanium nitride). Titanium nitride is particularly suitable, particularly in atomic
layer deposition. For example, titanium nitride has low electrical resistance (eg, as compared to
polysilicone) and / or can be deposited as a very thin layer (eg, as compared to polysilicone).
[0024]
In an alternative embodiment, the first electrode layer and / or the second electrode layer
comprises a metal conductive material. In particular, the metal conductive material is at least one
material selected from the group comprising Ni (nickel), Cu (copper), W (tungsten), Pt (platinum),
Ir (iridium), and Al (aluminum). May be included. For example, the metal may be an alloy of these.
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[0025]
In other embodiments, the first dielectric film and / or the second dielectric film comprises
processing residues such as carbon or chlorine residues. These residues may be residues of
precursors used in the ALD process. This indicates that the CMUT was manufactured using
atomic layer deposition. Residues can be detected using, for example, XPS (X-ray photoelectron
spectroscopy) or SIMS (other sorting methods such as secondary ion mass spectrometry).
[0026]
In another embodiment, the at least one patterned layer and / or film breaks abruptly or
discontinuously on the side. In other words, the top and sides of the layer are substantially
perpendicular to one another. This indicates that the CMUT was manufactured using patterning.
Ideally, the top and sides of the layers are perpendicular (90 °) or perpendicular to one another.
However, in practice, the layer may have some slope or the slope may be intentionally applied
because the patterning (especially etching) process is not perfect. Also, the etch rates of the
individual materials are not equal. Thus, when patterning (especially etching) a stack of layers
having different properties, the top and side surfaces of the layers are not perfectly
perpendicular at their ends. For example, an overhang structure may be formed. Accordingly, it is
understood that the substantially vertical angle is 70 ° to 110 ° (90 ° ± 20 °), 80 ° to 100
° (90 ° ± 10 °), or 85 ° to 95 ° (90 ° ± 5 °). It may be done.
[0027]
In another embodiment, the second electrode layer is patterned to be smaller than the first
electrode layer. This indicates that the CMUT was manufactured using "top-bottom" patterning.
Thus, a characteristic pyramid structure, in particular a step pyramid structure, is provided.
[0028]
In another embodiment, the CMUT further includes at least one conductive via extending in a
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direction perpendicular to the top surface of the layer from the first electrode layer and / or the
second electrode layer. Thus, the conductive vias are perpendicular or perpendicular to the
deposited layer. In this way, electrical connection can be provided to the first electrode, the
second electrode, or both. For example, the conductive vias may be electrically connected to the
ASIC below the CMUT.
[0029]
In another embodiment, the CMUT further includes a deposited layer and a dielectric layer
covering the film. In particular, the dielectric layer covers the top and sides of the deposited layer
and film with substantially the same coverage. This shows that CMUT provides very good step
coverage, especially using atomic layer deposition. In particular, the vertical portion of the
dielectric layer may extend substantially perpendicular to the deposited layer and / or the film.
As mentioned above, the substantially vertical angle is 70 ° to 110 ° (90 ° ± 20 °), 80 ° to
100 ° (90 ° ± 10 °), or 85 ° to 95 ° (90 ° ± 5 °) It may be understood that there is.
[0030]
These and other aspects of the invention will be described and become apparent with reference
to the embodiments described hereinafter.
[0031]
1a-j show a method of manufacturing a CMUT according to a first embodiment.
FIG. 1 j shows a schematic cross-sectional view of a CMUT according to the first embodiment. 2aj show a method of manufacturing a CMUT according to a second embodiment. FIG. 2j shows a
cross-sectional view of a CMUT according to a second embodiment. 3a-h show a method of
manufacturing a CMUT according to a third embodiment. FIG. 3h shows a schematic crosssectional view of a CMUT according to a third embodiment. FIG. 4 shows a graph of CMUT
dielectric constant (epsilon) versus relative acoustic output pressure. FIG. 5 shows an exemplary
graph of the electric field across the dielectric versus the current flowing through the dielectric.
[0032]
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1a-j show a method of manufacturing a CMUT 100 according to a first embodiment. In
particular, FIGS. 1 b-j show schematic top-bottom (from above) after all functional CMUT layers
have been deposited in one process sequence (see FIG. 1 a) by using atomic layer deposition
(ALD) Bottom) shows the processing flow.
[0033]
The method starts with a process sequence using ALD (see FIG. 1a). First, a first electrode layer
10 is deposited on a substrate (not shown) or dielectric layer 11. In the embodiment shown in
FIG. 1 a, the dielectric layer 11 is provided or deposited between the substrate and the first
electrode layer 10. The dielectric layer 11 is the first layer on the substrate in this example. In
this case, the dielectric layer may for example be composed of (silicon) oxide or (silicon) nitride,
in particular in the case of processing on an ASIC where a planarization step is often used to
create a smooth surface. It may be done that way. However, the dielectric layer 11 may be
omitted. In this case, a first dielectric film 20 is deposited on the first electrode layer 10 and a
sacrificial layer 30 is deposited on the first dielectric film 20. The sacrificial layer 30 can be
removed later to form the transducer cavity. Next, a second dielectric layer 40 is deposited on the
sacrificial layer 30. Subsequently, a second electrode layer 50 is deposited on the second
dielectric film 40. In the embodiment of FIG. 1 a, an additional dielectric layer 51 is deposited on
the second electrode layer 50. The dielectric layer 51 covers or protects the second electrode
layer 50, particularly when a sacrificial etch is performed to remove the sacrificial layer 30.
However, the dielectric layer 51 may be omitted. The deposition steps described above are
performed by atomic layer deposition (ALD). In this way, a stack of alternating layers of dielectric
material and conductive material is provided (see FIG. 1a). Thus, a single run of an ALD
apparatus in which all CMUT functional layers (AL-ALD CMUTs) can be performed in a single
process sequence, ie multiple (processing or deposition) steps can be performed without the
wafer leaving the ALD apparatus. Deposited in (operation). Thus, individual materials can be
stacked on top of each other in one process sequence, but in this process sequence, every
material is deposited in individual (processing or deposition) steps. This process or process
sequence is also referred to as a full layer ALD (AL-ALD) CMUT process.
[0034]
The method further comprises patterning at least one of the stacked layers and films 10, 20, 30,
40, 50, 51. An example of such patterning is described with reference to FIGS. 1b-d. The
manufacturing method uses "top-to-bottom" patterning. Top-to-bottom (top to bottom) patterning
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provides a characteristic pyramid structure, in particular a CMUT with a step pyramid structure
(typical cross sections can be confirmed by analysis methods using, for example, FIB or SEM
cross sections) . The at least one patterned layer and / or film breaks abruptly or discontinuously
on its side. In other words, the top and sides of the layer are substantially orthogonal to one
another. This indicates that the CMUT was manufactured using patterning. Ideally, the top and
sides of the layers are orthogonal (90 °) to one another. However, in practice, the layer may
have some slopes or may be intentionally sloped because the patterning (especially etching)
process is not perfect. Also, the etch rates of the individual materials are not equal. Thus, when
patterning (especially etching) a stack of layers having different properties, the top and side
surfaces of the layers are not perfectly square at the edges. For example, an overhang structure
may be formed. Thus, substantially perpendicular (orthogonal) is 70 ° to 110 ° (90 ° ± 20
°), 80 ° to 100 ° (90 ° ± 10 °), or 85 ° to 95 ° (90 ° ± 5 °) It can be understood as an
angle.
[0035]
In this first embodiment, as can be seen from FIG. 1 b, the patterning comprises a first step of
patterning the second electrode layer 50. This is performed using a first etch mask (denoted
"Mask 1"). In this way, the lateral dimension (in a direction parallel to the upper surface of the
layer or the upper surface of the substrate) of the second electrode 50 is determined. In this
example, the second dielectric film 40 (and the additional dielectric layer 51 on the second
electrode layer 50) is also patterned in the first step of patterning. As can be seen from the
figure, the second electrode layer 50 is patterned to be smaller than the first electrode layer 10.
For example, the second electrode layer 50 may be patterned in the form of a ring electrode. This
is beneficial for acoustic performance. As shown in FIG. 1 c, the patterning further comprises a
second step of patterning the sacrificial layer. This is performed using a second etch mask
(denoted "Mask 2"). In this way, the lateral dimension (in a direction parallel to the upper surface
of the layer or the upper surface of the substrate) of the cavity of the CMUT can be determined.
Furthermore, as shown in FIG. 1 d, the patterning includes a (separate) third step of patterning
the first electrode layer 10. This is performed using a third etch mask (denoted "Mask 3"). In this
way, the lateral dimension (in a direction parallel to the upper surface of the layer or the upper
surface of the substrate) of the first electrode 30 is determined. In this example, the first
dielectric film 20 is also patterned in the third step of patterning. In this example, only the
dielectric layer 11 on the substrate is not patterned. Thus, most deposited layers and films
(except dielectric layer 11) are patterned. Here, the patterning process after ALD deposition is
completed. All deposited functional CMUT layers and films 10, 20, 30, 40, 50, 51 are in the
patterned state.
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[0036]
In a subsequent step, and with reference to FIG. 1e, the method comprises depositing a dielectric
layer 60 covering the deposited layer and the films 10, 20, 30, 40, 50, 51. This deposition step
can be performed again using atomic layer deposition (ALD). Alternatively, other techniques such
as PECVD can be used. The dielectric layer 60 covers the top and side surfaces of the deposited
layer and film 10, 20, 30, 40, 50, 51 with substantially the same coverage (eg, the thickness of
the horizontal portion of the dielectric layer 60 and the dielectric layer) The thickness of the
vertical portion of 60 is substantially the same). This gives a very good step coverage. In other
words, the vertical portions of the dielectric layer 60 and the horizontal portions of the dielectric
layer 60 have approximately the same coverage or thickness (see FIG. 1e). The vertical portion
(in the direction perpendicular to the top surface of the layer or the top surface of the substrate)
of the dielectric layer 60 extends substantially perpendicular to the deposited layer and the films
10, 20, 30, 40, 50, 51. Ideally, the vertical portion of dielectric layer 60 is perpendicular (90 °)
or perpendicular to the deposited layer and / or film. However, in practice the dielectric layer 60
has some slope. Thus, the vertical portions of the dielectric layer 60 are not perfectly at right
angles. Thus, the substantially vertical angle may be 70 ° to 110 ° (90 ° ± 20 °), 80 ° to
100 ° (90 ° ± 10 °), or 85 ° to 95 ° (90 ° ± 5 °). It can be understood that there is.
[0037]
Next, the method etches the sacrificial layer 30 (see FIG. 1g), providing the etch holes 32, in
particular a plurality of etch holes (for example three or more), to form the cavity 35 (see FIG.
1f). And removing the sacrificial layer 30. Provision of the etching holes 32 is performed using a
fourth etching mask (denoted as "mask 4"). The etching holes 32 are provided in the dielectric
layer 60. The height of the cavity (in the direction perpendicular to the top of the layer or the top
of the substrate) is determined by the thickness of the sacrificial layer 30 removed. Subsequently,
referring to FIG. 1h, an additional layer 70 covering the dielectric layer 60, in particular an
additional dielectric layer may be provided. The additional layer 70 closes or blocks the etching
holes 32.
[0038]
Furthermore, the method includes providing at least one conductive via 15, 55 respectively
extending from the first electrode layer 10 and the second electrode layer 50 in a direction
perpendicular to the top surface of the layer (or the top surface of the substrate). . Thus, the
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conductive vias 15, 55 are perpendicular or perpendicular to the deposited layer. In this
example, this is done by providing the etch holes 62 and filling the etch holes 62 with a
conductive material to form the conductive vias 15, 55. Here, the first etching holes 62 are
provided so as to be connected to the first electrode layer 10 (through the additional layer 70,
the dielectric layer 60, and the first dielectric film 20). The second etching hole 62 is provided so
as to be connected to the second electrode layer 50 (through the dielectric layer 60 and the
additional layer 70). The first etching holes 62 are filled with a conductive material to form the
vias 15 from the first electrode layer 10. The second etch holes 62 are filled with a conductive
material to form the vias 55 from the second electrode layer 50. In addition, conductive portions
16, 56 are provided respectively for connecting vias 15, 55 to an external electrical connection
(for example connection to ASIC and / or power supply, eg for connection to a bias voltage or to
a cable or wirebond) Be In this way, both the first electrode 10 and the second electrode 50 are
provided with an electrical connection (e.g. to the ASIC below the CMUT). It should also be
understood that only the first etch hole or the second etch hole may be provided. For example,
conductive vias 15 from the first electrode 10 may be formed in the substrate.
[0039]
FIG. 1 j shows a schematic cross-sectional view of the CMUT 100 according to the first
embodiment. The CMUT 100 of FIG. 1j was manufactured, in particular, using the method
described above with reference to FIG. The CMUT 100 is formed on the first (bottom) electrode
layer 10 on the substrate (not shown), the first dielectric film 20 on the first electrode layer 10,
and the first dielectric film 20. Cavity 35, a second dielectric film 40 covering the cavity 35, and
a second (top) electrode layer 50 on the second dielectric film 40. Optionally, CMUT 100 may
include dielectric layer 11 and dielectric layer 51. Most deposited layers and films are patterned.
In this embodiment, all deposited CMUT functional layers and films 10, 20, 30, 40, 50 are
patterned. Thus, each deposited CMUT functional layer and film 10, 20, 30, 40, 50 is patterned.
The second electrode layer 50 is patterned to be smaller than the first electrode layer 10 (eg,
patterned in the form of a ring electrode), which is beneficial for acoustic performance. The
second electrode layer 50 is patterned to be smaller than the cavity 35. The cavity 35 is
patterned to be smaller than the first electrode layer 10. This provides a distinctive (stepped)
pyramidal structure. CMUT 100 further includes a dielectric layer 60 covering the deposited
layers and films 10, 20, 30, 40, 50. The dielectric layer 60 covers the top and side surfaces of the
deposited layer and film 10, 20, 30, 40, 50 with substantially the same coverage or thickness as
described above. The vertical portions of the dielectric layer 60 extend substantially
perpendicularly to the deposited layers 10, 20, 30, 40, 50. CMUT 100 further includes an
additional layer 70 covering dielectric layer 60. In particular, the additional layer 70 is much
thicker, for example more than two times, or more than five times more compared to other layers
or films (e.g. ). Furthermore, the CMUT includes conductive vias 15 extending from the first
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electrode layer 10 in a direction (vertical direction in FIG. 1j) orthogonal to the top surface of the
layer. The CMUT 100 also includes conductive vias 55 extending from the second electrode layer
50 in a direction (vertical direction in FIG. 1j) orthogonal to the top surface of the layer. The
CMUT 100 further includes conductive portions 16, 56 for connecting vias 15, 55 to an external
electrical connection (eg, to an ASIC and / or a power supply, eg, for connection to a bias voltage,
or to a cable or wirebond). Each contains.
The vias 15, 55 extend in the vertical direction (perpendicular to the top of the layer or
substrate) and the conductive portions 56 extend in the horizontal direction (parallel to the top
of the layer or substrate).
[0040]
2a-j show a method of manufacturing a CMUT according to a second embodiment. In this
embodiment, the substrate 1 comprises an ASIC 2 embedded in the substrate 1 and conductive
vias 15 in the substrate 1. Alternatively, the ASIC 2 may be attached to the substrate 1. The
method starts with depositing a first electrode layer 10 on a substrate 1. Thereafter, the first
dielectric film 20 is deposited on the first electrode layer 10, and the sacrificial layer 30 is
deposited on the first dielectric film 20. The sacrificial layer 30 can be removed later to form the
transducer cavity. Subsequently, a second dielectric film 40 is deposited on the sacrificial layer
30. Next, a second electrode layer 50 is deposited on the second dielectric film 40. Each of these
deposition steps is performed by atomic layer deposition (ALD). Doing so provides a stack of
alternating layers of dielectric material and conductive material (see FIG. 2b). Thus, all CMUT
functional layers (AL-ALD CMUTs) are deposited in a single process sequence.
[0041]
The method further comprises patterning all deposited layers and films 10, 20, 30, 40, 50, in
particular all deposited CMUT functional layers 10, 20, 30, 40, 50. In this embodiment, the
patterning comprises the first step of patterning the second electrode layer 50 (see FIG. 2c), the
sacrificial layer 30 and the first electrode 10, and the first dielectric film 20 and the second
dielectric. And (2) a second step (see FIG. 2 d) of patterning the body film 40. Thus, in this
embodiment, the sacrificial layer 30 and the first electrode layer 10 are patterned in a common
process. The first step of patterning the second electrode layer 50 is performed using a first
etching mask (mask 1). The second patterning step may be performed using a second etching
mask (Mask 2). As can be seen, the second electrode layer 50 is patterned to be smaller than the
04-05-2019
15
first electrode layer 10 (e.g., in the form of a ring electrode). Here, the patterning process is
completed.
[0042]
In the next step, referring to FIG. 2e, the method comprises depositing a dielectric layer 60
covering the deposited layer and the films 10, 20, 30, 40, 50. This deposition step is again
performed using atomic layer deposition (ALD). The dielectric layer 60 covers the top and sides
of the deposited layer and film 10, 20, 30, 40, 50 with substantially the same coverage or
thickness as described above. This gives a very good step coverage. In other words, the vertical
portion of the dielectric layer 60 and the horizontal portion of the dielectric layer 60 have
approximately the same coverage or thickness (see FIG. 2e). The vertical portions of the dielectric
layer 60 extend substantially perpendicularly to the deposited layers 10, 20, 30, 40, 50.
[0043]
Next, the method includes removing the sacrificial layer 30 by providing the etch holes 32 (see
FIG. 2f) and etching the sacrificial layer 30 to form the cavities 35 (see FIG. 2g). The etching
holes 32 are provided in the dielectric layer 60 and the second dielectric insulating film 40. The
etching holes 32 can be provided using a third etching mask (mask 3). Thereafter, referring to
FIG. 2h, an additional layer 70 covering the dielectric layer 60, in particular an additional
dielectric layer may be provided. The additional layer 70 closes or blocks the etching holes 32.
[0044]
In addition, the method includes providing a conductive via 55 extending in a direction
perpendicular to the top surface of the layer from the second electrode layer 50. Thus, the
conductive vias 55 are perpendicular or perpendicular to the top surface of the layer. In this
example, this is done by providing the etch holes 62 (see FIG. 2i) and filling the etch holes 62
with a conductive material to form the conductive vias 55 (see FIG. 2j). Provision of the etching
holes 62 can be performed using a fourth etching mask (mask 4). Conductive vias 15 to the first
electrode 10 are formed in the substrate 1. In addition, conductive portions 56 are provided for
external electrical connection from vias 55. This may be performed by depositing a conductive
layer on the additional layer 70 and then patterning the conductive layer. This may be performed
using a fifth etch mask (Mask 5).
04-05-2019
16
[0045]
FIG. 2j shows a cross-sectional view of a CMUT 100 according to a second embodiment. The
CMUT 100 of FIG. 2j was manufactured specifically using the method described above with
reference to FIG. The CMUT 100 covers the first electrode layer 10 on the substrate 1, the first
dielectric film 20 on the first electrode layer 10, the cavity 35 formed above the first dielectric
film 20, and the cavity 35. A second dielectric film 40 and a second electrode layer 50 on the
second dielectric film 40 are included. Optionally, the CMUT 100 may include the dielectric layer
11 on the substrate and the dielectric layer 51 on the second electrode layer 50 as described in
connection with the first embodiment. In the embodiment shown in FIG. 2j, all deposited CMUT
functional layers and films 10, 20, 30, 40, 50 are patterned. The second electrode layer 50 is
smaller or smaller (in a direction parallel to the top surface of the layer or substrate) in the
lateral dimension, eg smaller diameter in the case of a circular shape, than the first electrode
layer 10 and the cavity It is patterned to have This provides a distinctive (stepped) pyramidal
structure. CMUT 100 further includes a dielectric layer 60 covering the deposited layers and
films 10, 20, 30, 40, 50. The dielectric layer 60 covers the top and side surfaces of the deposited
layer and film 10, 20, 30, 40, 50 with substantially the same coverage, as described above. The
vertical portions of the dielectric layer 60 extend substantially perpendicular to the deposited
layers 10, 20, 30, 40, 50. CMUT 100 further includes an additional layer 70 covering dielectric
layer 60. In particular, the additional layer 70 is much thicker, for example more than twice or
more than five times, compared to other layers or films (e.g. about 1 .mu.m thick for a layer 40
with a thickness of about 200 nm) Layer 70). It should be noted that in FIG. 2j, the additional
layer 70 is only schematically shown and may follow the shape of the layer 60, similar to the
additional layer 70 depicted with respect to FIG. 1j. Furthermore, the CMUT includes conductive
vias 55 extending from the second electrode layer 50 in a direction (vertical direction in FIG. 2j)
perpendicular to the top surface of the layer. CMUT 100 further includes conductive portions 56
for making vias 55 external electrical connections (eg, to an ASIC and / or power supply, eg, for
connection to a bias voltage, or to a cable or wirebond). The CMUT 100 also includes conductive
vias 15 from the first electrode 10. Conductive vias 15 are formed in the substrate 1. The vias
15, 55 extend in the vertical direction (perpendicular to the top surface of the layer or substrate)
and the conductive portions 56 extend in the horizontal direction (parallel to the top surface of
the layer or substrate).
[0046]
3a-h show a method of manufacturing a CMUT according to a third embodiment. The method of
04-05-2019
17
the third embodiment of FIGS. 3a-h is similar to the method of the second embodiment of FIGS.
2a-j. However, as compared to the second embodiment, the process of FIG. 2C for separately
patterning the second electrode layer 50 is omitted. Thus, fewer etching masks are used in the
third embodiment.
[0047]
In the third embodiment, the substrate 1 includes an ASIC 2 incorporated in the substrate 1 and
conductive vias 15 in the substrate 1. The method starts with depositing a first electrode layer
10 on a substrate 1. Next, the first dielectric film 20 is deposited on the first electrode layer 10,
and the sacrificial layer 30 is deposited on the first dielectric film 20. The sacrificial layer 30 can
be removed later to form the transducer cavity. Subsequently, a second dielectric film 40 is
deposited on the sacrificial layer 30. Next, a second electrode layer 50 is deposited on the second
dielectric film 40. Each of these deposition steps is performed by atomic layer deposition (ALD).
In this way, a stack of alternating layers of dielectric material and conductive material is provided
(see FIG. 3a). Thus, all CMUT functional layers (AL-ALD CMUTs) are deposited in a single process
sequence.
[0048]
The method further comprises patterning all deposited layers and films 10, 20, 30, 40, 50, in
particular all deposited CMUT functional layers 10, 20, 30, 40, 50. In this embodiment, the
patterning comprises a common step of patterning the second electrode layer 50, the sacrificial
layer 30, and the first electrode layer 10 (see FIG. 3b). Therefore, in this embodiment, all the
deposited layers (the second electrode layer 50, the second dielectric insulating layer 40, the
sacrificial layer 30, the first dielectric insulating layer 20, and the first electrode layer 10) are
formed. It is patterned in a common process. As can be seen from the figure, all deposited layers
and films 10, 20, 30, 40, 50 have the same horizontal dimension (in a direction parallel to the
top surface of the layer or substrate), e.g. diameter if circular. A common patterning step may be
performed using the first etch mask (Mask 1). Here, the patterning process ends.
[0049]
In a subsequent step, referring to FIG. 3c, the method comprises depositing a deposited layer and
a dielectric layer 60 covering the films 10, 20, 30, 40, 50. This deposition step is again
04-05-2019
18
performed using atomic layer deposition (ALD). The dielectric layer 60 covers the top and sides
of the deposited layer and film 10, 20, 30, 40, 50 with substantially the same coverage. This
gives a very good step coverage. In other words, the vertical portion of dielectric layer 60 and the
horizontal portion of dielectric layer 60 have approximately the same coverage or thickness (see
FIG. 3c).
[0050]
Subsequently, the method comprises removing the sacrificial layer 30 by providing the etching
holes 32 (see FIG. 3 d) and etching the sacrificial layer 30 to form the cavities 35 (see FIG. 3 e).
The etching holes 32 are provided in the dielectric layer 60 and the second dielectric insulating
film 40. As shown in FIGS. 3d and 3e, the etching holes 32 are preferably not provided in the
second electrode layer 50, but in the adjacent part thereof. The etch holes 32 extend from the
dielectric layer 60 to the second dielectric film 40 past the second electrode layer 50, as shown
by the dotted lines in FIGS. 3d and 3e. The etching holes 32 may be provided using a second
etching mask (mask 2). Thereafter, referring to FIG. 3f, an additional layer 70 covering the
dielectric layer 60, in particular an additional dielectric layer may be provided. The additional
layer 70 closes or blocks the etching holes 32.
[0051]
In addition, the method includes providing a conductive via 55 extending in a direction
perpendicular to the top surface of the layer from the second electrode layer 50. Thus, the
conductive vias 55 are perpendicular or perpendicular to the deposited layer. In this example,
this is done by providing etch holes 62 (see FIG. 3g) and filling the etch holes 62 with a
conductive material (see FIG. 3h) to form conductive vias 55. Provision of the etching holes 62
can be performed using a third etching mask (mask 3). Conductive vias 15 to the first electrode
10 are formed in the substrate 1. In addition, conductive portions 56 are provided for external
electrical connection from vias 55. This may be performed by depositing a conductive layer on
the additional layer 70 and then patterning the conductive layer. This may be performed using a
fourth etch mask (Mask 4).
[0052]
FIG. 3 h shows a schematic cross-sectional view of a CMUT 100 according to a third embodiment.
04-05-2019
19
The CMUT 100 of FIG. 3 h was manufactured using the method described above with particular
reference to FIG. The CMUT 100 covers the first electrode layer 10 on the substrate 1, the first
dielectric film 20 on the first electrode layer 10, the cavity 35 formed above the first dielectric
film 20, and the cavity 35. A second dielectric film 40 and a second electrode layer 50 on the
second dielectric film 40 are included. Optionally, the CMUT 100 may have a dielectric layer 11
on the substrate and a dielectric layer 51 on the second electrode layer 50 as described in
connection with the first embodiment. In the embodiment shown in FIG. 3h, all CMUT functional
layers and films 10, 20, 30, 40, 50 are patterned in a common step. Thus, all deposited layers
and films 10, 20, 30, 40, 50 are patterned to have the same horizontal dimension (in a direction
parallel to the top surface of the layer or substrate), eg diameter in the case of a circle. Thus, no
distinctive (stepped) pyramidal structure is provided in this embodiment. CMUT 100 further
includes a dielectric layer 60 covering the deposited layers and films 10, 20, 30, 40, 50. As
mentioned above, the dielectric layer 60 covers the top and sides of the deposited layers and
films 10, 20, 30, 40, 50 with substantially the same coverage. The vertical portions of the
dielectric layer 60 extend substantially perpendicularly to the deposited layers 10, 20, 30, 40,
50. CMUT 100 further comprises an additional layer 70 covering dielectric layer 60. In
particular, the additional layer 70 is much thicker, for example more than twice or more than five
times, compared to other layers or films (e.g. about 1 .mu.m thick for a layer 40 with a thickness
of about 200 nm) Layer 70). It should be noted that in FIG. 3h, the additional layer 70 is only
schematically shown and may follow the shape of the layer 60, similar to the additional layer 70
depicted with respect to FIG. 1j. Furthermore, the CMUT includes conductive vias 55 extending
from the second electrode layer 50 in a direction (vertical direction in FIG. 3h) perpendicular to
the top surface of the layer. CMUT 100 further includes conductive portions 56 for making vias
55 external electrical connections (eg, to an ASIC and / or power supply, eg, for connection to a
bias voltage, or to a cable or wirebond). The CMUT 100 also includes conductive vias 15 from
the first electrode 10. Conductive vias 15 are formed in the substrate 1. The vias 15, 55 extend
in the vertical direction (perpendicular to the top surface of the layer or substrate) and the
conductive portions 56 extend in the horizontal direction (parallel to the top surface of the layer
or substrate).
[0053]
Preferably, in any of the illustrated embodiments, the first dielectric film 20 and the second
dielectric film 40 are each a first layer comprising an oxide, a second layer comprising a high-k
material, and It includes a third layer containing an oxide. Thus, the dielectric insulating layers
20, 40 comprise an oxide layer (O), a high-k layer, and a further oxide layer (O). In other words,
the high-k layer is sandwiched between two oxide layers (especially silicone oxide). In particular,
the high-k material may be aluminum oxide (Al 2 O 3) and / or hafnium oxide (HfO 2). For
example, an (alternating layer) laminate of oxide-aluminum oxide-oxide (abbreviated OAO) can be
04-05-2019
20
provided. In another example, the second layer includes a first sublayer comprising aluminum
oxide, a second sublayer comprising hafnium oxide, and a third sublayer comprising aluminum
oxide. In this way, an (alternate layer) laminate of oxide-aluminum oxide-haunium oxidealuminum oxide-oxide (abbreviated OAHAO) can be provided.
[0054]
The dielectric constant of the deposited layer generally depends on the density of the material
and thus on the deposition or process settings such as the process temperature (the temperature
at which the layer is formed). Aluminum oxide has a dielectric constant (k or ε r) of 7-9,
depending on the deposition or processing settings. For example, the dielectric constant of
aluminum oxide can be 7.5 (eg, deposited at a low temperature of about 265 ° C.), 8 (eg,
deposited at a high temperature of about 350 ° C.), or 9. Depending on the deposition or
processing settings, the hafnium oxide has a dielectric constant (k or ε r) of 12-27. For example,
the dielectric constant of hafnium oxide can be 14, 20, or 25. The dielectric constant of the
aluminum oxide-hafnium oxide-aluminum oxide laminate may be, for example, 10.
[0055]
Preferably, in each embodiment, each of the first electrode layer 10 and the second electrode
layer 50 includes a nonmetallic conductive material (for example, a semiconductor). For example,
non-metallic conductive materials include TiN (titanium nitride), TaN (tantalum nitride), TaCN,
IrO 2 (iridium oxide), ITO (indium tin oxide), LaNiO 3, and SrRuO 3 (strontium ruthenate) It may
be at least one (or only one) material selected from the group. These materials are suitable for
atomic layer deposition. In particular, the non-metallic conductive material may be titanium
nitride (TiN). Titanium nitride (TiN) has a conductivity of about 30 to 70 μΩ cm and is
considered to be an excellent conductor. Alternatively, polysilicon (having a conductivity of about
500 μΩcm) may be used. The material of the electrode layer is, for example, at least one
selected from the group including, in particular, Ni (nickel), Cu (copper), W (tungsten), Pt
(platinum), Ir (iridium), and Al (aluminum) It should be understood that any other conductive
material, such as a metal, including only one) material may be used. For example, the metal can
be an alloy of these. For example, aluminum has a conductivity of about 3 μΩcm. In any case,
the conductive materials (metals and nonmetals) of the electrodes must be suitable for deposition
by ALD (e.g. in an ALD apparatus).
[0056]
04-05-2019
21
The dielectric layer 60 and / or the additional layer 70 may be or include, for example, an oxide
(especially silicon oxide), a nitride (especially silicon nitride), or a combination of both. For
example, dielectric layer 60 may be or include a combination of (silicon) oxide and (silicon)
nitride. For example, the additional layer 70 may be (silicon) nitride or include. However, it
should be understood that any other suitable dielectric material may be used. The dielectric layer
60 may be deposited, for example, by ALD or PECVD. The additional layer 70 can in particular be
deposited by PECVD because of its high thickness. In particular, the sacrificial layer 30 may be
composed of a different material (with different etching characteristics) than the dielectric
insulating layer 20,40. By doing this, the sacrificial layer can be selectively removed.
[0057]
FIG. 4 shows a graph of CMUT dielectric constant (epsilon) versus relative acoustic output
pressure. FIG. 4 is based on simulation. All dimensions (gap thickness, dielectric thickness etc)
are considered constant. Black circles indicate hafnium oxide (HfO 2) deposited by ALD (here,
epsilon 14). White circles indicate ONO. The diamonds indicate aluminum oxide (Al 2 O 3)
deposited by ALD (here epsilon 8). As can be seen from the graph, assuming that a bias voltage
can be applied, the high-k material nearly doubles the output pressure (e.g., about 70% for
Al2O3).
[0058]
FIG. 5 shows an exemplary graph of the electric field across the dielectric versus the current
flowing through the dielectric. A graph of field versus current is shown for ONO and high
temperature aluminum oxide Al 2 O 3, respectively. As can be seen from FIG. 8, compared to
ONO, the leak current of aluminum oxide Al 2 O 3 (high temperature) is small for the same
electric field value. Also, compared to ONO, aluminum oxide Al 2 O 3 (high temperature) can be
applied with at least the same bias voltage.
[0059]
Providing high-k dielectric layers and layer stacks fabricated using atomic layer deposition (ALD)
techniques can significantly improve CMUT performance (eg, reduce operating voltage and / or
04-05-2019
22
(acoustic) output By increasing the pressure). In particular, by providing non-metal electrodes
(eg, TiN) rather than metal electrodes, ALD technology offers the unique option of depositing all
CMUT functional layers in a single process step. Thus, dielectric stacks with higher effective
dielectric constants provide performance enhancements that may be accompanied by similar or
reduced drift of the CMUT due to charge trapping in the dielectric layer. The full layer ALD (ALALD) CMUT process is very beneficial as it provides the option to further improve CMUT
performance by adjusting the properties of each layer and their boundaries. The AL-ALD
technique with top-bottom patterning ensures high quality interfaces of the individual dielectrics
and requires less operator intervention.
[0060]
In CMUT, it can be detected whether the layer was deposited by ALD, and in one example, when
deposited by ALD, the first dielectric film 20 and / or the second dielectric film 40 is carbon or
chlorine Includes processing residues such as residue. Residues can be detected, for example,
using XPS (X-ray photoelectron spectroscopy) or other sorting methods, such as SIMS (secondary
ion mass spectrometry) or the like. In another example, the second layer of dielectric insulating
layers 20, 40 has a thickness of less than 100 nm. Such very thin high-k layers can be provided
(only) by using ALD.
[0061]
In the method described herein (AL-ALD), essentially all layer stacks are deposited and then
patterned (and finally a dielectric layer is also deposited, which also serves to close the cavity).
Thus, for a CMUT manufactured by this method, all or most of the dielectric layer is removed or
absent in the area adjacent to the membrane in the cross-sectional view of the CMUT. However,
for CMUTs fabricated using other methods (non-ALD), such as sputtering, in the cross-sectional
view of the CMUT, all or most of the dielectric layers comprising the CMUT are present in the
region adjacent to the thin film.
[0062]
Layers deposited by ALD (in particular of Al 2 O 3 and / or HfO 2) may exhibit one or more of
the following features: (1) For example for sputtered Al 2 O 3, the step coverage of ALD
deposited Al 2 O 3 is very good and very conformal (shape match). This is detectable, for
04-05-2019
23
example, in a (cross-sectional view) SEM. (2) ALD oxide allows better control of the charging
effect, and the leakage current is much lower (as ALD oxide has no pinholes), which appears in
the capacity-voltage measurement (CV curve) . (3) The composition of Al 2 O 3 is different (eg,
compared to sputtered Al 2 O 3) and can be detected by RBS and / or XPS. (4) Typical processing
residues such as carbon (which can not be found for example in sputtered Al 2 O 3) are detected
by XPS or SIMS.
[0063]
Merely by way of example, SIMS (secondary ion mass spectrometry) can be used to detect the
difference between sputtered aluminum oxide and aluminum oxide deposited by ALD. For
example, argon is used in the sputtering process and some residue is found in the sputtered layer
(e.g. several percent). This can be easily detected by SIMS (secondary ion mass spectrometry).
[0064]
Compared to the oxide layer (O) in the ONO dielectric insulating layer, the function of the oxide
layer (O) in the OAO dielectric insulating layer is largely different. An oxide layer (O) in the ONO
dielectric insulation layer is present for electrical reasons. In the absence of the oxide layer (O),
the CMUT device is heavily charged, which significantly reduces performance. In practice, the
minimum thickness of a single O layer (deposited by PECVD) is about 50 nm. An oxide layer (O)
in the OAO is present for processing reasons. In the absence of the oxide layer (ie, only the
alumina layer), it has been found that the layer is subjected to very high mechanical stress,
significant thin film deformation occurs, and the CMUT becomes inoperable. However, the use of
the OAO dielectric insulation layer results in low stress levels. The oxide layer can be thin.
Furthermore, the OAO dielectric insulation layer has better electrical behavior as compared to
the alumina layer alone.
[0065]
Capacitive microfabricated transducers have been described as CMUTs in connection with
ultrasound. However, capacitive microfabricated transducers may also be used in other
applications, such as pressure sensors or pressure transducers.
04-05-2019
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[0066]
The capacitive microfabricated transducer, in particular the CMUT, may be or comprise a single
cell, in particular a CMUT cell. However, capacitive micromachined transducers, in particular
CMUTs, may comprise an array of cells, in particular CMUT cells. The capacitive microfabricated
transducer, in particular the CMUT and / or its layer may have a circular shape. However, other
shapes such as squares or hexagons can also be used.
[0067]
While the present invention has been illustrated and described in detail in the drawings and the
foregoing, it should be understood that such illustration and description are illustrative or
exemplary and not restrictive. The invention is not limited to the disclosed embodiments. By
analyzing the drawings, the disclosure and the appended claims, those skilled in the art can
understand and practice other variations of the disclosed embodiments in practicing the claimed
invention.
[0068]
In the claims, the term & quot; comprising & quot; does not exclude other elements or steps, and
the element does not exclude a plurality. A single element or other unit may fulfill the functions
of several items recited in the claims. The mere fact that certain measures are recited in mutually
different dependent claims does not mean that a combination of these measures can not be
preferably used.
[0069]
Any reference signs in the claims should not be construed as limiting the scope.
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