JP2008288813

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DESCRIPTION JP2008288813
An object of the present invention is to improve both the withstand voltage of the interelectrode
insulating film and the charge accumulation suppression of the interelectrode insulating film. A
lower electrode M0E is formed on a semiconductor substrate 1S via an insulating film 2,
insulating films 5 and 7 are formed to cover the lower electrode M0E, and an upper electrode
M1E is formed on an insulating film 7, Insulating films 9, 11, 13 are formed so as to cover upper
electrode M1E, and a cavity VR is formed between insulating films 5 and 7 between lower
electrode M0E and upper electrode M1E. The lower electrode M0E, the insulating film 5, the
cavity VR, the insulating film 7, and the upper electrode M1E form an ultrasonic transducer. In
the insulating film 5, at least a portion in contact with the lower electrode M0E is made of silicon
oxide, in the insulating film 7 at least a portion in contact with the upper electrode M1E is made
of silicon oxide, at least one of the insulating films 5 and 7 is the upper electrode M1E and It
includes a silicon nitride film 5b located between lower electrode M0E and not in contact with
either upper electrode M1E or lower electrode M0E. [Selected figure] Figure 17
Semiconductor device
[0001]
The present invention relates to a semiconductor device, and more particularly to a technology
that is effective when applied to an ultrasonic transducer.
[0002]
Ultrasonic transducers are used, for example, in diagnostic devices such as tumors in a human
body by transmitting and receiving ultrasonic waves.
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[0003]
Conventionally, ultrasonic transducers that use vibration of a piezoelectric material have been
used, but with advances in MEMS technology in recent years, a vibrating portion with a structure
in which a cavity is sandwiched between upper and lower two-layer electrodes is placed on a
silicon substrate Capacitive Micromachined Ultrasonic Transducers (CMUTs) manufactured have
been actively developed for practical use.
[0004]
The CMUT has advantages such as a wider usable frequency band of ultrasound or higher
resolution than conventional transducers using a piezoelectric body.
In addition, since CMUTs are manufactured using LSI processing technology, microprocessing is
possible.
In particular, when one ultrasonic element is arranged in an array and each element is controlled
independently, CMUT is considered to be essential.
The reason is that wiring to each element is required, and the number of wirings in the array may
be a huge number, but it is possible that the wiring and further to one chip of the signal
processing circuit from the ultrasonic transmitting and receiving unit. Mixed loading is also
possible with CMUT.
[0005]
The technology relating to such an ultrasonic transducer is described, for example, in US Pat. No.
6,271,620 B1 (Patent Document 1).
[0006]
Moreover, the sensor which pinched ¦ interposed the insulating film and the hollow part by the
upper and lower electrodes is disclosed by Unexamined-Japanese-Patent No. 2003-28740
(patent document 2) and Unexamined-Japanese-Patent No. 2004-361115 (patent document 3).
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U.S. Pat. No. 6,271,620 B1 Japanese Patent Laid-Open No. 2003-28740 Japanese Patent LaidOpen No. 2004-361115
[0007]
According to the study of the inventor, the following was found.
[0008]
The basic structure and operation of the CMUT examined by the present inventor will be
described with reference to FIG.
FIG. 19 is a cross-sectional view of a main part of a CMUT cell examined by the present inventor.
In FIG. 19, M0E is a lower electrode, 105a is a silicon oxide film, VR is a cavity, 107a is a silicon
oxide film, M1E is an upper electrode, 9, 11, 13 are insulating films, upper and lower electrodes
(upper electrode M1E and The hollow portion VR is sandwiched between the lower electrode
M0E). The silicon oxide film 105a, the upper electrode M1E, and the insulating films 9, 11 and
13 formed thereon constitute a membrane, and the membrane vibrates.
[0009]
An operation of transmitting (transmitting) an ultrasonic wave will be described. When a DC
voltage and an AC voltage are superimposed on the upper electrode M1E and the lower electrode
M0E, an electrostatic force acts between the upper electrode M1E and the lower electrode M0E,
and the silicon oxide film 105a forming the membrane on the cavity VR, the upper electrode
M1E and The insulating films 9, 11 and 13 (the laminated films thereof) vibrate at the frequency
of the applied AC voltage, and transmit ultrasonic waves.
[0010]
Conversely, when ultrasonic waves are received, the pressure of the ultrasonic waves reaching
the surface of the device vibrates the membrane on the cavity VR. Since the distance between the
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upper electrode M1E and the lower electrode M0E changes due to this vibration, ultrasonic
waves can be detected as a change in electric capacitance between the upper electrode M1E and
the lower electrode M0E. That is, when the distance between the upper and lower electrodes
changes, the electric capacitance between the upper and lower electrodes changes, and current
flows. By detecting this current, ultrasonic waves can be detected.
[0011]
As apparent from the above operating principle, in the CMUT, ultrasonic waves are transmitted
by utilizing vibration of the membrane due to electrostatic force caused by voltage application
between the upper and lower electrodes and change in electric capacity between the upper and
lower electrodes due to the vibration and Receive. Generally, when a direct current and an
alternating current are combined, the voltage applied between the upper and lower electrodes is
as high as 100 V or more, so improvement of the withstand voltage between the upper and lower
electrodes becomes an important issue.
[0012]
In particular, in the lower electrode M0E, the electric field is easily concentrated at the upper
surface end 121, and the electric field of the insulating film is increased at the upper surface end
121 of the lower electrode M0E as compared to the upper surface. The current increases. In the
upper electrode M1E, the electric field easily concentrates on the step portion 123 of the lower
surface generated due to the cavity VR, the electric field of the insulating film increases, and the
leakage current increases in the path 124 indicated by the arrow in FIG. . When the silicon oxide
films 105a and 107a are used as the insulating film between the upper and lower electrodes, this
tendency is particularly remarkable, and the dielectric breakdown voltage is lowered. This is
considered to be due to Fowler-Nordheim tunneling conduction, in which the conduction
mechanism of the silicon oxide film strongly depends on the electric field.
[0013]
For this reason, it is desirable to improve the withstand voltage between the upper and lower
electrodes and to improve the performance of the semiconductor device.
[0014]
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On the other hand, it is also conceivable to use a silicon nitride film instead of the silicon oxide
films 105a and 107a as an insulating film between the upper and lower electrodes.
Since the silicon nitride film has a dielectric constant larger than that of the silicon oxide film, the
physical film thickness can be increased when the capacitance of the insulating film is the same,
and the reduction in breakdown voltage can be suppressed.
[0015]
However, as a result of the study of the present inventor, a single layer silicon nitride film is used
instead of the silicon oxide film 105a and the silicon oxide film 107a, and the upper and lower
electrodes (upper electrode M1E and lower electrode M0E) and silicon nitride film are used. In
the case of the cell structure in direct contact, charge is accumulated in the silicon nitride film
due to the leak current between the upper and lower electrodes, and the voltage-capacitance
characteristic changes with the increase of the operation time, and as a result, it is clear that the
transmission / reception sensitivity fluctuates. became.
[0016]
For this reason, it is desirable to suppress the fluctuation of the transmission / reception
sensitivity caused by the charge accumulation of the insulating film to improve the performance
of the semiconductor device.
[0017]
Further, in the above-mentioned Japanese Patent Application Laid-Open No. 2003-28740 (Patent
Document 2) and the above-mentioned Japanese Patent Application Laid-Open No. 2004361115 (Patent Document 3), the hollow portion is sandwiched between upper and lower
electrodes through an insulating film using MEMS technology. Although a sensor for detecting
pressure or acceleration from a change in capacitance between electrodes is disclosed, the
purpose is only to detect a physical quantity such as pressure or acceleration, and a high voltage
is applied to transmit an ultrasonic wave. It has no active function.
Therefore, the problem of charge accumulation in the inter-electrode insulating film due to the
leak current between the upper and lower electrodes and the fluctuation of detection
performance due to this caused by the application of the high operating voltage as described
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above does not occur.
For this reason, in the above-mentioned Japanese Patent Application Laid-Open Nos. 200328740 and 2004-361115, there is no description about a device structure for suppressing
charge accumulation in the interelectrode insulating film and a method of manufacturing the
same. Absent.
[0018]
An object of the present invention is to provide a technology capable of improving the
performance of a semiconductor device.
[0019]
Another object of the present invention is to provide a technique capable of achieving both the
improvement of the withstand voltage of the interelectrode insulating film and the suppression of
the charge accumulation of the interelectrode insulating film.
[0020]
The above and other objects and novel features of the present invention will be apparent from
the description of the present specification and the accompanying drawings.
[0021]
The outline of typical ones of the inventions disclosed in the present application will be briefly
described as follows.
[0022]
According to the present invention, the first electrode and the second electrode are disposed
opposite to each other via the first insulating film and the second insulating film stacked so as to
have a cavity therebetween, and the first insulating film on the first electrode side is arranged.
The second insulating film on the second electrode side is made of silicon oxide and at least a
portion in contact with the first electrode is made of silicon oxide, and at least a portion of the
first insulating film and the second insulating film One side includes a silicon nitride layer portion
located between the first electrode and the second electrode and not in contact with either the
first electrode or the second electrode.
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[0023]
The effects obtained by typical ones of the inventions disclosed in the present application will be
briefly described as follows.
[0024]
The performance of the semiconductor device can be improved.
[0025]
Further, it is possible to achieve both the improvement of the withstand voltage of the
interelectrode insulating film and the suppression of the charge accumulation of the
interelectrode insulating film.
[0026]
Before describing the present invention in detail, the meanings of terms in the present
application will be described as follows.
[0027]
1.
The semiconductor substrate refers to silicon other semiconductor single crystal substrates,
quartz substrates, sapphire substrates, glass substrates, other insulation, anti-insulation or
semiconductor substrates, etc. and composite substrates thereof used for manufacturing
semiconductor integrated circuits.
[0028]
In the following embodiments, when it is necessary for the sake of convenience, it will be
described by dividing into a plurality of sections or embodiments, but they are not unrelated to
each other unless specifically stated otherwise, one is the other And some or all of the variations,
details, and supplementary explanations.
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Further, in the following embodiments, when referring to the number of elements (including the
number, numerical value, quantity, range, etc.), it is particularly pronounced and clearly limited
to a specific number in principle. Except for the specific number, it is not limited to the specific
number, and may be more or less than the specific number.
Furthermore, in the following embodiments, the constituent elements (including element steps
and the like) are not necessarily essential unless explicitly stated or considered to be obviously
essential in principle. Needless to say.
Similarly, in the following embodiments, when referring to the shapes, positional relationships
and the like of components etc., the shapes thereof are substantially the same unless particularly
clearly stated and where it is apparently clearly not so in principle. It is assumed that it includes
things that are similar or similar to etc.
The same applies to the above numerical values and ranges.
[0029]
Hereinafter, embodiments of the present invention will be described in detail based on the
drawings.
In all the drawings for describing the embodiments, members having the same functions are
denoted by the same reference numerals, and the repetitive description thereof will be omitted.
Further, in the following embodiments, the description of the same or similar parts will not be
repeated in principle unless particularly required.
[0030]
In the drawings used in the embodiments, hatching may be omitted to make the drawing easy to
see even if it is a sectional view.
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Further, even a plan view may be hatched to make it easy to see the drawing.
[0031]
First Embodiment A semiconductor device according to the present embodiment is, for example,
an ultrasonic transducer (ultrasonic transmission / reception sensor) manufactured using MEMS
(Micro Electro Mechanical System) technology.
[0032]
FIG. 1 is an overall plan view of a semiconductor chip 1 constituting the semiconductor device of
the present embodiment.
[0033]
The semiconductor chip 1 has a first main surface (upper surface, front surface) and a second
main surface (lower surface, back surface) located opposite to each other along the thickness
direction.
FIG. 1 shows a plan view (that is, a top view) of the first main surface side of the semiconductor
chip 1.
[0034]
As shown in FIG. 1, the planar shape of the semiconductor chip 1 is formed, for example, in a
rectangular shape.
The length of the semiconductor chip 1 in the longitudinal direction (second direction Y) is, for
example, about 4 cm, and the length of the semiconductor chip 1 in the short direction (first
direction X) is, for example, about 1 cm.
However, the planar dimension of the semiconductor chip 1 is not limited to this, and can be
variously changed. For example, the length in the longitudinal direction (second direction Y) is
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about 8 cm and the length in the short direction (first direction X) There are various sensors,
such as about 1.5 cm.
[0035]
A CMUT region (CMUT cell region, sensor region, sensor cell array, vibrator array) CA and a
plurality of bonding pads (hereinafter referred to as pads) BP1 and BP2 are disposed on the first
main surface of the semiconductor chip 1. .
[0036]
In the CMUT (Capacitive Micromachined Ultrasonic Transducer) area CA, a plurality of lower
electrode wires (lower electrode, first electrode) M0 and a plurality of upper electrode wires
(upper electrode, second) orthogonal thereto are formed. An electrode M1 and a plurality of
vibrators (CMUT cells, sensor cells, corresponding to vibrators 20 described later) are arranged.
[0037]
The plurality of lower electrode wirings M0 are formed to extend along the longitudinal direction
(second direction Y) of the semiconductor chip 1, and for example, 16 in the short direction (first
direction X) of the semiconductor chip 1. Channels (hereinafter also referred to as ch) are
arranged side by side.
[0038]
Lower electrode interconnections M0 are electrically connected to pads BP1, respectively.
A plurality of pads BP1 are provided along the short side of the semiconductor chip 1 so as to
correspond to the lower electrode wirings M0 in the vicinity of both ends of the CMUT region CA
in the longitudinal direction (second direction Y) of the semiconductor chip 1 They are arranged
side by side.
[0039]
The plurality of upper electrode wires M1 are formed to extend along the short direction (first
direction X) of the semiconductor chip 1, respectively. For example, 192 ch in the longitudinal
direction (second direction Y) of the semiconductor chip 1 They are arranged side by side.
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[0040]
The upper electrode wires M1 are electrically connected to the pads BP2, respectively.
A plurality of pads BP2 are provided along the long side of the semiconductor chip 1 so as to
correspond to the upper electrode wiring M1 in the vicinity of both ends of the semiconductor
chip 1 in the short direction (first direction X). They are arranged side by side.
[0041]
The vibrator (corresponding to the vibrator 20 described later) is, for example, a capacitive
transducer, and is disposed at the intersection of the lower electrode wiring M0 and the upper
electrode wiring M1.
That is, a plurality of transducers (corresponding to the transducers 20 described later) are
regularly arranged in a matrix (matrix, array) form in the CMUT region CA.
In the CMUT area CA, for example, about 50 vibrators are arranged in parallel at the intersection
of the lower electrode wiring M0 and the upper electrode wiring M1.
[0042]
Therefore, the CMUT area CA is an area in which a plurality of sensor cells or CMUT cells
(corresponding to the vibrator 20 described later) are formed, and the semiconductor chip 1 has
a main surface (a CMUT area CA in which a plurality of CMUT cells are formed). It is a
semiconductor device which has on the 1st principal surface).
[0043]
Next, FIG. 2 to FIG. 4 are main part plan views (main part enlarged plan views) of the
semiconductor chip 1 and FIGS. 5 and 6 are main part sectional views of the semiconductor chip
1.
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FIG. 2 shows a planar layout of the lower electrode wiring M0, and other components are not
shown. FIG. 3 is a diagram in which the planar layout of the cavity VR and the hole 10 is further
added (overlapped) to FIG. 2, and the components other than the lower electrode wiring M0, the
cavity VR and the hole 10 are not shown. . FIG. 4 is a diagram in which the planar layout of
upper electrode wire M1 and pads BP1 and BP2 is further added (superimposed) to FIG. 3, lower
electrode wire M0, cavity VR, hole 10, upper electrode wire M1 and pad BP1. , BP2 are not
shown. 5 substantially corresponds to the cross-sectional view taken along the line A-A of FIG. 4,
and FIG. 6 substantially corresponds to the cross-sectional view taken along the line B-B of FIG. 2
to 4 show an area in which the lower electrode wiring M0 is 2ch and the upper electrode wiring
M1 is 2ch in the CMUT region CA, and 12 pieces are formed at each intersection of the lower
electrode wiring M0 and the upper electrode wiring M1. Although the top view at the time of
arrange ¦ positioning the vibrator ¦ oscillator 20 is shown, the number of the vibrator ¦ oscillators
20 arrange ¦ positioned to each intersection is not limited to this.
[0044]
A semiconductor substrate 1S constituting the semiconductor chip 1 is made of, for example,
silicon (Si) single crystal, and a first main surface (upper surface, surface) 1Sa and a second main
surface (lower surface) opposite to each other along the thickness direction , Back surface) 1Sb.
As shown in FIGS. 2 to 6, on the first main surface 1Sa of the semiconductor substrate 1S, the
plurality of vibrators (capacitive elements) described above via an insulating film (third insulating
film) 2 made of, for example, silicon oxide , CMUT cell, ultrasonic transducer cell) 20 are
arranged (formed).
[0045]
As shown in FIG. 4, each of the plurality of vibrators 20 is formed, for example, in a planar
hexagonal shape, and is arranged, for example, in a honeycomb shape. As a result, the plurality of
transducers 20 can be disposed at high density, and sensor performance can be improved.
[0046]
Further, each vibrator 20 includes a lower electrode (lower electrode portion, first electrode)
M0E, an upper electrode (upper electrode portion, second electrode) M1E provided to face the
lower electrode M0E, and an interelectrode therebetween And a cavity VR interposed
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therebetween.
[0047]
The lower electrode M0E is formed at a portion where the upper electrode wiring M1 overlaps in
plan view in the lower electrode wiring M0.
That is, lower electrode M0E of each vibrator 20 is formed by a part of lower electrode
interconnection M0, and a portion of lower electrode interconnection M0 overlapping in plan
view with cavity VR (ie, located below cavity VR) Part) is the lower electrode M0E. The lower
electrode wiring M0 is a conductor pattern for the lower electrode of the vibrator 20, and the
entire lower electrode wiring M0 (the pattern itself of the lower electrode wiring M0) can be
regarded as an electrode (lower electrode, first electrode) .
[0048]
Lower electrode wiring M0 (lower electrode M0E) is formed of a patterned (patterned) conductor
film 3, and for example, a laminated film in which a titanium nitride (TiN) film, an aluminum (Al)
film and a titanium nitride film are laminated in order from the bottom It consists of A tungsten
(W) film may be used instead of the titanium nitride film.
[0049]
An insulating film (embedded insulating film) 4a is embedded between the adjacent lower
electrode wirings M0 (between the lower electrodes M0E). That is, insulating film 4a is formed to
fill the space between adjacent lower electrode wires M0 (between lower electrodes M0E), and
the upper surface of insulating film 4a and the upper surface between lower electrode wires M0
(between lower electrodes M0E) And a substantially flat surface is formed. The insulating film 4a
is made of, for example, silicon oxide.
[0050]
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Lower electrode wiring M0 (lower electrode M0E) is formed on first main surface 1Sa of
semiconductor substrate 1 with insulating film 2 interposed therebetween, and insulating film 2
(semiconductor substrate 1) so as to cover lower electrode wiring M0 (lower electrode M0E).
Insulating film (first insulating film) 5 is formed (deposited) on the first main surface 1Sa). As
described above, since the insulating film 4a is embedded between the lower electrode wires M0
(between the lower electrodes M0E), the insulating film 5 is deposited (formed) on the lower
electrode wires M0 (lower electrode M0E) and the insulating film 4a. ). In the present
embodiment, the insulating film 5 is formed of a laminated film of a silicon oxide film 5a, a
silicon nitride film 5b, and a silicon oxide film 5c sequentially stacked from the lower side (lower
electrode wiring M0 side).
[0051]
An insulating film (second insulating film) 7 is formed (deposited) on the insulating film 5. In the
present embodiment, the insulating film 7 is formed of a single film (single film, single layer) of
the silicon oxide film 7a. The upper electrode M1E is provided on the insulating film 7 so as to
face the lower electrode M0E.
[0052]
The upper electrode M1E is formed in a portion where the lower electrode wiring M0 overlaps in
plan view in the upper electrode wiring M1. That is, the upper electrode M1E of each vibrator 20
is formed by a part of the upper electrode wiring M1, and a portion of the upper electrode wiring
M1 overlapping in plan with the lower electrode wiring M0 (ie, above the lower electrode wiring
M0 The upper electrode M1E is a portion located on the The planar shape of the upper electrode
M1E is formed in a substantially hexagonal shape, and the upper electrode wiring M1 is formed
in a wider pattern than the connecting portion M1C connecting the upper electrodes M1E. As
described above, the upper electrode wiring M1 includes the plurality of upper electrodes M1E
and the connecting portion M1C that connects the upper electrodes M1E adjacent in the first
direction X. The upper electrode wiring M1 is a conductor pattern for the upper electrode of the
vibrator 20, and the entire upper electrode wiring M1 (the combination of the upper electrode
M1E and the connecting portion M1C, the pattern itself of the upper electrode wiring M1) It can
also be regarded as an upper electrode, a second electrode).
[0053]
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The upper electrode wiring M1 including the upper electrode M1E and the coupling portion M1C
is formed of the patterned conductor film 8, and for example, a titanium nitride (TiN) film, an
aluminum (Al) film and a titanium nitride (TiN) film are sequentially stacked from the bottom Of
the laminated film. A tungsten film may be used instead of the titanium nitride film.
[0054]
The hollow portion VR is formed between the lower electrode M0E (lower electrode wire M0)
and the upper electrode M1E (upper electrode wire M1) (between opposing surfaces). The hollow
portion VR is formed between the insulating film 5 and the insulating film 7 so as to be
surrounded by the upper surface of the insulating film 5 and the lower surface of the insulating
film 7. The planar shape of the hollow portion VR is formed, for example, in a hexagonal shape.
The planar shape of the upper electrode M1E is also, for example, hexagonal. Also, the planar
pattern of the upper electrode M1E can be formed, for example, to be planarly included in the
planar pattern of the cavity VR.
[0055]
The insulating film 5 formed of a laminated film of the silicon oxide film 5a, the silicon nitride
film 5b and the silicon oxide film 5a is disposed between the lower electrode M0E and the cavity
VR, and between the upper and lower electrodes (the upper electrode M1E and the lower
electrode M0E Function) to ensure insulation resistance. The insulating film 7 is disposed
between the cavity VR and the upper electrode wiring M1 (upper electrode M1E), and has a
function of securing insulation resistance between the upper and lower electrodes together with
the insulating film 5.
[0056]
An insulating film 9 made of, for example, a silicon nitride film or the like is deposited (formed)
on the insulating film 7 so as to cover the upper electrode wiring M1 including the upper
electrode M1E and the coupling portion M1C. In the insulating films 7 and 9, in the vicinity of
the hexagonal portion of the hollow portion VR, holes (openings, through holes, through holes)
10 reaching the hollow portion VR are formed. The hole 10 is a hole (cavity portion for forming a
cavity portion VR by etching a sacrificial film pattern (sacrifice film pattern 6 described later)
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between the insulating film 5 and the insulating film 7 through the hole 10 as described later.
Holes for forming VR).
[0057]
An insulating film 11 made of, eg, a silicon nitride film is formed (deposited) on the insulating
film 9. A part of the insulating film 11 is in the hole 10, whereby the hole 10 is closed.
[0058]
An insulating film 13 made of a photosensitive polyimide film or the like is formed (deposited) on
the insulating film 11 as a protective film.
[0059]
In the insulating films 5, 7, 9, 11, 13, an opening (not shown) reaching a part of the lower
electrode wiring M0 is formed, and a part of the lower electrode wiring M0 exposed from the
opening is It is a pad BP1.
In addition, an opening (not shown) reaching a part of upper electrode wiring M1 is formed in
insulating films 9, 11, 13 and a part of upper electrode wiring M1 exposed from this opening is a
pad BP2 It has become. The pads BP1 and BP2 are terminals for input and output of the
semiconductor chip 1, and bonding wires and the like are electrically connected to the pads BP1
and BP2.
[0060]
Thus, the insulating film 5 and the insulating film 7 are interposed between the lower electrode
wiring M0 (lower electrode M0E) and the upper electrode wiring M1 (upper electrode M1E), and
are sandwiched between the lower electrode M0E and the upper electrode M1E. In the isolated
region, a cavity VR is provided between the insulating film 5 and the insulating film 7, the
insulating film 5 is interposed between the lower electrode M0E and the cavity VR, and the cavity
VR and the upper electrode M1E are provided. And the insulating film 7 is interposed
therebetween.
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[0061]
Each of a plurality of CMUT cells (vibrator 20) of the semiconductor chip 1 includes a lower
electrode M0E (lower electrode wiring M0), an upper electrode M1E (upper electrode wiring
M1), a lower electrode M0E (lower electrode wiring M0) and an upper It is an ultrasonic
transducer (variable capacity sensor) formed of the insulating film 5 between the electrodes M1E
(upper electrode wiring M1), the cavity VR and the insulating film 7.
That is, the insulating film 5 between the lower electrode M0E (lower electrode wiring M0) and
upper electrode M1E (upper electrode wiring M1) and the lower electrode M0E (lower electrode
wiring M0) and upper electrode M1E (upper electrode wiring M1) A capacitive element is formed
(configured) by the VR and the insulating film 7, and more specifically, an ultrasonic transducer
is formed (configured).
[0062]
Next, a method of manufacturing the semiconductor device of the present embodiment will be
described with reference to FIGS. 7 to 18 are main-portion cross-sectional views of the
semiconductor device in the present embodiment during the manufacturing process thereof, and
in FIGS. 7 to 18, FIGS. 7 to 13 are regions corresponding to FIG. 14 is a cross-sectional view (a
cross-sectional view at a position corresponding to the line A-A in FIG. 4), and FIGS. 14 to 18 are
cross-sectional views corresponding to the above-mentioned FIG. Sectional view).
[0063]
In order to manufacture the semiconductor chip 1, first, as shown in FIG. 7, a semiconductor
substrate (in this stage, a semiconductor thin plate in a substantially circular shape called a
semiconductor wafer in this stage) 1S is prepared. The semiconductor substrate 1S is made of,
for example, silicon single crystal, and has a first main surface (upper surface, front surface) 1Sa
and a second main surface (lower surface, back surface) 1Sb located opposite to each other along
the thickness direction. .
[0064]
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Next, over the entire surface of the first main surface 1Sa of the semiconductor substrate 1S, the
insulating film 2 made of, for example, a silicon oxide film or the like is formed (deposited). The
film thickness of the insulating film 2 can be, for example, about 800 nm.
[0065]
Next, a conductor film (conductor layer) 3 for lower electrode wiring formation is formed
(deposited) on the insulating film 2. The conductor film 3 is formed on the entire surface of the
first main surface 1Sa of the semiconductor substrate 1S. The conductor film 3 is made of a
metal film or a film showing metallic conductivity, and is made of, for example, a laminated film
of a titanium nitride (TiN) film, an aluminum (Al) film and a titanium nitride (TiN) film formed in
order from the bottom. . The aluminum film is made of a conductor film containing aluminum as
a main component, such as an aluminum single film or an aluminum alloy film. The conductor
film 3 can be formed by using, for example, a sputtering method. When the conductor film 3 is a
laminated film of a titanium nitride film, an aluminum film and a titanium nitride film, the
aluminum film is a main conductor film of the lower electrode wiring M0, so the film thickness of
the aluminum film is a titanium nitride film For example, the thickness of the aluminum film may
be about 600 nm, and the thickness of each titanium nitride film above and below the aluminum
film may be about 50 nm. Also, instead of the titanium nitride film, a stacked film of a titanium
(Ti) film and a titanium nitride film, a tungsten (W) film, or the like can be used.
[0066]
Next, as shown in FIG. 8, the conductor film 3 is patterned (processed) using a lithography
method, a dry etching method, or the like. The lower electrode wiring M0 (lower electrode M0E)
is formed by the patterned conductor film (conductor layer) 3.
[0067]
Thus, the lower electrode wiring M0 is formed on (the insulating film 2 on) the semiconductor
substrate 1S. The lithography method is a method of patterning a resist film into a desired
pattern by a series of steps of application of a resist film (photoresist film), exposure and
development.
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18
[0068]
Next, as shown in FIG. 9, an insulating film 4 such as a silicon oxide film is formed on the
semiconductor substrate 1S (on the insulating film 2) to cover the lower electrode wiring M0, for
example, by plasma CVD (Chemical Vapor Deposition). : Form (deposition) using a chemical vapor
deposition method or the like. At this time, the insulating film 4 is deposited to such a thickness
that the space between the adjacent lower electrode wirings M0 is sufficiently filled with the
insulating film 4.
[0069]
Next, as shown in FIG. 10, the insulating film 4 on the upper surface of the lower electrode
wiring M0 is removed by a CMP (Chemical Mechanical Polishing) method, an etch back method,
or the like to lower the electrode wiring M0. While exposing the upper surface of the insulating
film 4 between the adjacent lower electrode wirings M0. The insulating film 4 remaining between
the adjacent lower electrode wirings M0 serves as an insulating film (embedded insulating film)
4a filling the space between the lower electrode wirings M0.
[0070]
Next, as shown in FIG. 11, the lower electrode wiring M0 (ie, on the upper surface of the lower
electrode wiring M0 and the upper surface of the insulating film 4a filling the lower electrode
wiring M0) over the entire first surface of the semiconductor substrate 1S. The insulating film 5
is formed (deposited) so as to cover the lower electrode M0E) and the insulating film 4a filling
the space between the lower electrode wirings M0.
[0071]
In the present embodiment, the insulating film 5 is formed of a laminated film of a silicon oxide
film 5a, a silicon nitride film 5b and a silicon oxide film 5c in order from the bottom.
More specifically, silicon oxide film 5a is formed on the entire first main surface of
semiconductor substrate 1S (that is, on the upper surface of insulating film 4a filling the space
between lower electrode interconnection M0 and lower electrode interconnection M0) using
04-05-2019
19
plasma CVD or the like. (Deposition) Form (deposit) a silicon nitride film 5b on the silicon oxide
film 5a by plasma CVD or the like, and form (deposition) a silicon oxide film 5c on the silicon
nitride film 5b by plasma CVD or the like ). The film thickness (deposited film thickness) of the
silicon oxide film 5a is about 50 nm, the film thickness (deposited film thickness) of the silicon
nitride film 5b is about 175 nm, and the film thickness (deposited film thickness) of the silicon
oxide film 5c is about 50 nm It can be done.
[0072]
Next, as shown in FIG. 12, a sacrificial film made of, for example, an amorphous silicon film is
formed on the entire surface of the insulating film 5 of the first main surface 1Sa of the
semiconductor substrate 1S using plasma CVD or the like Then, the sacrificial film is patterned
by lithography and dry etching to form a sacrificial film pattern (a sacrificial film pattern for
forming a cavity) 6. The sacrificial film pattern 6 is formed on the insulating film 5 on the lower
electrode wiring M0 (lower electrode M0E). The sacrificial film pattern 6 is a pattern for forming
the cavity VR, and the planar shape of the sacrificial film pattern 6 is formed to be the same
planar shape as the cavity VR. Therefore, the sacrificial film pattern 6 is formed in the region
where the cavity VR is to be formed.
[0073]
Next, as shown in FIG. 13, the insulating film 7 is formed on the entire surface of the first main
surface 1Sa of the semiconductor substrate 1S (that is, on the insulating film 5) so as to cover the
surface of the sacrificial film pattern 6 accumulate. In the present embodiment, the insulating
film 7 is formed of a single film (single film, single layer) of the silicon oxide film 7a, and can be
formed using plasma CVD or the like. The film thickness (deposited film thickness) of the
insulating film 7 can be, for example, about 200 nm.
[0074]
Next, a conductor film (conductor layer) 8 for forming an upper electrode wiring is formed
(deposited) on the insulating film 7. The conductor film 8 is formed on the entire surface of the
first main surface 1Sa of the semiconductor substrate 1S. The conductor film 8 is formed of a
metal film or a film showing metallic conductivity, and is formed of, for example, a laminated film
of a titanium nitride (TiN) film, an aluminum (Al) film and a titanium nitride (TiN) film formed in
04-05-2019
20
order from the bottom. . The aluminum film is made of a conductor film containing aluminum as
a main component, such as an aluminum single film or an aluminum alloy film. The conductor
film 8 can be formed by using, for example, a sputtering method. Further, the thickness of the
conductor film 8 for forming the upper electrode wiring can be thinner than the thickness of the
conductor film 3 for forming the lower electrode wiring, for example, about 400 nm. When the
conductor film 8 is a laminated film of a titanium nitride film, an aluminum film and a titanium
nitride film, the aluminum film is a main conductor film of the upper electrode wiring M1 and
therefore, the film thickness of the aluminum film is a titanium nitride film For example, the film
thickness of the aluminum film can be about 300 nm, and the film thicknesses of the titanium
nitride films above and below the aluminum film can be about 50 nm. Also, instead of the
titanium nitride film, a stacked film of a titanium (Ti) film and a titanium nitride film, a tungsten
(W) film, or the like can be used.
[0075]
Here, FIG. 14 is a cross-sectional view of the main parts showing the same process step (the stage
where the conductive film 8 is formed) as in FIG. 13, and as described above, the regions
corresponding to FIG. In contrast to what has been shown, FIGS. 14 and the subsequent FIGS. 1518 show the regions corresponding to FIG. 6 above.
[0076]
After the conductor film 8 is formed as shown in FIGS. 13 and 14, the conductor film 8 is
patterned (processed) using a lithography method, a dry etching method or the like as shown in
FIG.
An upper electrode wiring M1 (upper electrode M1E and connection portion M1C) is formed by
the patterned conductor film 8. Thereby, the upper electrode wiring M1 is formed on the
insulating film 7.
[0077]
Next, as shown in FIG. 16, over the entire first surface 1Sa of the semiconductor substrate 1S
(that is, over the insulating film 7), the insulating film 9 is covered so as to cover the upper
electrode wiring M1 (upper electrode M1E). Form (deposit). The insulating film 9 is made of, for
example, a silicon nitride film, and can be formed using a plasma CVD method or the like. The
04-05-2019
21
thickness of the insulating film 9 can be, for example, about 500 nm.
[0078]
Next, holes (openings, through holes) 10 which reach the sacrificial film pattern 6 and expose a
part of the sacrificial film pattern 6 to the insulating films 9 and 7 by lithography and dry etching
are used. Form The hole 10 is formed at a position overlapping the sacrificial film pattern 6 in
plan view, and a portion of the sacrificial film pattern 6 is exposed at the bottom of the hole 10.
[0079]
Next, the sacrificial film pattern 6 is selectively etched through the holes 10 using, for example, a
dry etching method using xenon fluoride (XeF 2). Thereby, as shown in FIG. 17, the sacrificial
film pattern 6 is selectively removed, and the region where the sacrificial film pattern 6 was
present becomes a cavity VR, and a cavity is formed between the insulating film 5 and the
insulating film 7. A part VR is formed. That is, in the CMUT region CA, a cavity VR is formed
between opposing surfaces (a removal region of the sacrificial film pattern 6) of the lower
electrode wiring M0 (lower electrode M0E) and the upper electrode wiring M1 (upper electrode
M1E).
[0080]
Thus, by selectively etching the sacrificial film pattern 6 between the insulating films 5 and 7
through the holes 10, it is possible to form a cavity VR between the lower electrode wiring M0
and the upper electrode wiring M1. In addition to dry etching using xenon fluoride (XeF 2), the
sacrificial film pattern 6 can be etched by dry etching using ClF 3 or the like to form a cavity VR.
[0081]
In the lower electrode wiring M0, the portion facing the upper electrode wiring M1 through the
hollow portion VR is the lower electrode M0E, and in the upper electrode wiring M1, the portion
facing the lower electrode wiring M0 through the hollow portion VR is It is the upper electrode
M1E.
04-05-2019
22
[0082]
Next, as shown in FIG. 18, the insulating film 11 is formed (deposited) over the entire first
surface 1Sa of the semiconductor substrate 1S (that is, on the insulating film 9).
Thereby, a part of the insulating film 11 can be embedded in the hole 10 to close the hole 10.
The insulating film 11 is made of, for example, a silicon nitride film or the like, and can be
formed using a plasma CVD method or the like. In addition, the thickness of the insulating film
11 can be, for example, about 800 nm. Thus, the capacitive vibrator 20 is formed.
[0083]
Thereafter, an opening (not shown) for pad BP1 such that a part of lower electrode wiring M0 is
exposed to insulating films 11, 9, 7 and 5 is also formed in insulating films 11 and 9 for upper
electrode wiring M1. An opening (not shown) for the pad BP2 partially exposed is formed by
lithography and dry etching. Then, as shown in FIGS. 5 and 6, the insulating film 13 made of a
photosensitive polyimide film or the like is formed on the entire surface of the first main surface
1Sa of the semiconductor substrate 1S (ie, on the insulating film 11). Openings (not shown) for
the pads BP1 and BP2 are formed in the insulating film 13 such that portions of the lower
electrode wiring M0 and the upper electrode wiring M1 are exposed by exposure and
development processing and the like. A part of lower electrode interconnection M0 exposed from
the opening of insulating films 5, 7, 9, 11, 13 becomes the above-mentioned pad BP1, and one of
upper electrode interconnection M1 exposed from the openings of insulating films 9, 11, 13 The
part becomes the above-mentioned pad BP2. Thereafter, the semiconductor chip 1 can be
manufactured by cutting out individual chip regions from the semiconductor substrate 1S
(semiconductor wafer) by dicing.
[0084]
Next, the effects of the present embodiment will be described in more detail.
[0085]
In the ultrasonic transducer configured as shown in FIGS. 1 to 6, the insulating film 7, the upper
electrode M1E, and the insulating films 9, 11 and 13 on the upper side thereof constitute a
04-05-2019
23
membrane, and the membrane vibrates. .
When DC voltage and AC voltage are superimposed and applied to lower electrode wiring M0
(lower electrode M0E) and upper electrode wiring M1 (upper electrode M1E), lower electrode
wiring M0 (lower electrode M0E) and upper electrode wiring M1 (upper electrode M1E) Of the
alternating voltage applied by the insulating film 7, the upper electrode wiring M1 (upper
electrode M1E), and (the laminated film of) the insulating films 9, 11 and 13 constituting the
membrane on the cavity VR. It vibrates in the direction crossing the first main surface 1Sa of the
semiconductor substrate 1S at a frequency, and an ultrasonic wave can be transmitted (sent). A
voltage can be applied to the lower electrode wiring M0 through the pad BP1, and a voltage can
be applied to the upper electrode wiring M1 through the pad BP2.
[0086]
Conversely, when ultrasonic waves are received, the pressure of the ultrasonic waves reaching
the surface of the CMUT area CA of the semiconductor chip 1 vibrates the membrane on the
cavity VR of each transducer 20. Since the distance (interval) between the upper electrode M1E
and the lower electrode M0E changes due to this vibration, ultrasonic waves can be detected as a
change in electric capacitance between the upper electrode M1E and the lower electrode M0E.
That is, when the distance (interval) between the upper and lower electrodes (upper electrode
M1E and lower electrode M0E) changes, the capacitance between the electrodes changes and
current flows. By detecting this current, ultrasonic waves can be detected.
[0087]
In the CMUT region CA, the vibration of the membrane by the electrostatic force caused by the
voltage application between the upper electrode M1E and the lower electrode M0E and the
capacitance change between the upper electrode M1E and the lower electrode M0E due to the
vibration of the membrane Although transmission (transmission) and reception are performed,
the voltage applied between the upper electrode M1E and the lower electrode M0E is a high
voltage of, for example, 100 V or more. Therefore, it is important to improve the withstand
voltage between the upper electrode M1E (upper electrode wiring M1) and the lower electrode
M0E (lower electrode wiring M0).
[0088]
04-05-2019
24
FIG. 19 is a cross-sectional view of main parts of a semiconductor device of a first comparative
example examined by the inventor, and FIG. 20 is a cross-sectional view of main parts of a
semiconductor device of a second comparative example examined by the inventor. All correspond
to the above-mentioned FIG. 5 of the present embodiment.
[0089]
Unlike the present embodiment, in the first comparative example of FIG. 19, a film corresponding
to the insulating film 5 of the present embodiment is a single film of the silicon oxide film 105 a,
and the insulating film 7 of the present embodiment is used. The equivalent is a single film of the
silicon oxide film 107a.
Unlike the present embodiment, in the second comparative example shown in FIG. 20, a film
corresponding to the insulating film 5 of the present embodiment is a single film of the silicon
nitride film 105b, and the insulating film 7 of the present embodiment is used. The equivalent is
a single film of the silicon nitride film 107b. Except the insulating films 5 and 7, the
semiconductor devices of the first comparative example of FIG. 19 and the second comparative
example of FIG. 20 have almost the same configuration as the semiconductor device of this
embodiment. , I omit the explanation here.
[0090]
When a voltage is applied between the opposing electrodes, the electric field tends to be
concentrated at the pointed portion rather than the flat surface of the electrode. Therefore, in the
lower electrode wiring M0 (lower electrode M0E), the electric field tends to be concentrated on
the upper surface end 121 of the lower electrode wiring M0 (lower electrode M0E) shown in FIG.
In the above path, for example, the path 122 indicated by the arrow in FIG. In the upper
electrode wiring M1 (upper electrode M1E), the electric field easily concentrates on the step
(corner, step corner) 123 of the lower surface generated due to the cavity VR. In the path
described above, for example, the path 124 indicated by the arrow in FIG. 19, leakage current
between the upper and lower electrodes and dielectric breakdown are likely to occur.
[0091]
04-05-2019
25
The insulating film (corresponding to the insulating films 5 and 7 of the present embodiment)
interposed between the upper electrode wiring M1 and the lower electrode wiring M0 is made of
the silicon oxide film 105a and the silicon oxide film 105a as in the first comparative example of
FIG. In the case of only 107a, the dielectric breakdown voltage between the lower electrode
wiring M0 and the upper electrode wiring M1 is lowered due to the electric field concentration at
the step portion 123 of the upper surface end portion 121 of the lower electrode wiring M0 and
the lower surface of the upper electrode wiring M1. The leakage current between the upper and
lower electrodes is increased in the path 122 and the path 124 in FIG. This is considered to be
due to Fowler-Nordheim tunneling conduction, in which the conduction mechanism of the silicon
oxide film strongly depends on the electric field.
[0092]
On the other hand, the insulating film (corresponding to the insulating films 5 and 7 of the
present embodiment) interposed between the upper electrode wiring M1 and the lower electrode
wiring M0 is a silicon nitride film as in the second comparative example of FIG. When only the
electrodes 105b and 107b are formed, the upper electrode M1E and the lower electrode M0E are
in direct contact with the silicon nitride films 107a and 105a, so the upper electrode M1E (upper
electrode wiring M1) and the lower electrode M0E (lower electrode wiring M0) Charges are
accumulated in the silicon nitride films 105b and 107b (one or both of the silicon nitride films
105b and 107b) due to the leak current between them). When charges are accumulated in the
silicon nitride films 105b and 107b, the voltage-capacitance characteristic of the vibrator 20
constituted of the upper electrode M1E and the lower electrode M0E changes, and as a result, the
transmission / reception sensitivity of the CMUT region CA fluctuates. This was found by the
study of the inventor.
[0093]
On the other hand, in the present embodiment, as also shown in FIGS. 5 and 6, the insulating film
5 is formed between the upper electrode wiring M1 (upper electrode M1E) and the lower
electrode wiring M0 (lower electrode M0E). , 7 intervene, the insulating film 5 is a laminated film
of a silicon oxide film 5a, a silicon nitride film 5b and a silicon oxide film 5c, and the insulating
film 7 is a silicon oxide film 7a. Therefore, in the present embodiment, both the silicon oxide film
and the silicon nitride film are interposed between the upper electrode wiring M1 (upper
electrode M1E) and the lower electrode wiring M0 (lower electrode M0E), and the lower
electrode M0E is formed. The upper surface of (lower electrode interconnection M0) is in contact
with the silicon oxide film (here, silicon oxide film 5a) and not in contact with the silicon nitride
04-05-2019
26
film (here, silicon nitride film 5b), and upper electrode M1E (upper electrode interconnection
M1) The lower surface of the) is in contact with the silicon oxide film (here, the silicon oxide film
7a) and not in contact with the silicon nitride film (here, the silicon nitride film 5b).
[0094]
FIG. 21 is a graph showing the result of evaluating the withstand voltage of the insulating film
between the upper electrode wiring M1 and the lower electrode wiring M0 in the CMUT cell. The
horizontal axis of the graph of FIG. 21 corresponds to the voltage (arbitrary unit: arbitrary unit)
applied between the upper electrode M1E and the lower electrode M0E, and the vertical axis of
the graph of FIG. 21 corresponds to the upper electrode M1E (upper electrode wiring M1
Corresponding to the leak current (arbitrary unit: arbitrary unit) between the lower electrode
M0E and the lower electrode M0E (lower electrode wiring M0). However, the vertical axis in FIG.
21 is shown by logarithm. Further, in the graph of FIG. 21, in the case of the present embodiment
of the structure as shown in FIG. 5 and FIG. 6 (indicated by the solid line in the graph of FIG. 21
as the present embodiment ) In the case of the first comparative example of the structure as
shown in FIG. 21 (indicated by dotted lines in the graph of FIG. 21 as first comparative
example ). The thickness of the silicon oxide film 7a for the insulating film 7 in the case of
the present embodiment shown in the graph of FIG. 21 and the thickness of the silicon oxide
film 107a in the case of the first comparative example are the same. And the total thickness
of the laminated film of the silicon oxide film 5a, the silicon nitride film 5b and the silicon oxide
film 5c for the insulating film 5 in the case of the present embodiment and the oxidation in
the case of the first comparative example . The thickness of the silicon film 105a is adjusted
so that the capacitance value between the upper electrode M1E and the lower electrode M0E is
the same in the case of the present embodiment and the case of the first comparative example.
[0095]
As apparent from the graph of FIG. 21, between the upper electrode wiring M1 and the lower
electrode wiring M0, as compared with the first comparative example using only the silicon oxide
film as the insulating film between the upper electrode wiring M1 and the lower electrode wiring
M0. In the present embodiment using the laminated film of the silicon oxide film 5a, the silicon
nitride film 5b and the silicon oxide film 5c for the insulating films 5 and 7 and the silicon oxide
film 7a, the dielectric breakdown voltage between the upper and lower electrodes is It has been
greatly improved. This is the Fowler in the case of the first comparative example in which the
conduction mechanism of the insulating film between the upper electrode wiring M1 (upper
electrode M1E) and the lower electrode wiring M0 (lower electrode M0E) is formed only of the
04-05-2019
27
silicon oxide films 105a and 107a. From the Nordheim type, it is considered that the conduction
mechanism through the trap in the silicon nitride film 5 b is called Poole-Frenkel type in this
embodiment. The pool-Frenkel type conduction is less susceptible to the electric field
concentration at the upper end 121 of the lower electrode wiring M0 and the step 123 at the
lower surface of the upper electrode wiring M1 because the electric field dependency of the
insulating film is small.
[0096]
Thus, in the present embodiment, the silicon nitride film 5b is interposed between the upper and
lower electrodes, whereby the insulating film between the upper electrode wiring M1 (upper
electrode M1E) and the lower electrode wiring M0 (lower electrode M0E) is formed. The electric
conduction mechanism becomes a pool-frenkel type, and is not affected by the electric field
concentration at the portion corresponding to the upper surface end portion 121 and the step
portion 123, and the leakage current It is possible to suppress or prevent the occurrence or the
dielectric breakdown. Thereby, the performance of the semiconductor chip 1 provided with the
CMUT cell array can be improved, and the manufacturing yield can be improved.
[0097]
FIG. 22 is a graph showing the result of measuring the shift amount of the capacity-voltage curve
by applying a drive voltage at the time of actual operation for a long time between the upper
electrode M1E and the lower electrode M0E of the CMUT cell. The horizontal axis of the graph of
FIG. 22 corresponds to the voltage application time (arbitrary unit: arbitrary unit) between the
upper electrode M1E and the lower electrode M0E, and the vertical axis of the graph of FIG. It
corresponds to the voltage shift (arbitrary unit: arbitrary unit) of (C-V curve). However, the
horizontal axis of FIG. 22 is shown by logarithm. Further, in the graph of FIG. 22, in the case of
the present embodiment of the structure as shown in FIG. 5 and FIG. 6 (indicated by black circles
as the present embodiment in the graph of FIG. In the case of the first comparative example
of the structure as shown (indicated by a white circle as the first comparative example in the
graph of FIG. 22) and in the case of the second comparative example of the structure as shown in
FIG. In the graph of FIG. 22, indicated by white triangles as second comparative example )
is shown. Note that the respective thicknesses of the insulating films 5 and 7 in the case of the
present embodiment and the respective thicknesses of the silicon oxide films 105 a and 107 a
in the case of the first comparative example shown in the graph of FIG. The respective
thicknesses of the silicon nitride films 105 b and 107 b in the case of comparative example
2 mean the case where the capacitance value between the upper electrode M 1 E and the lower
04-05-2019
28
electrode M 0 E is in the present embodiment and first comparative example . It is
adjusted so that it becomes the same in the case of and "the 2nd comparative example."
[0098]
FIG. 23 is a graph schematically showing a capacitance-voltage curve (C-V curve) before and
after applying a drive voltage during actual operation for a long time between the upper
electrode M1E and the lower electrode M0E. In the graph of FIG. 23, the initial capacitancevoltage curve (C-V curve) is indicated by a solid line, and the capacitance-voltage curve after the
drive voltage during the actual operation is applied for a long time between the upper electrode
M1E and the lower electrode M0E A CV curve) is schematically shown by a dotted line, and a
shift amount from an initial capacitance-voltage curve (CV curve) is a voltage shift Vsf. The value
of this voltage shift Vsf corresponds to the vertical axis of the graph of FIG.
[0099]
The insulating film between the upper electrode wiring M1 (upper electrode M1E) and the lower
electrode wiring M0 (lower electrode M0E) is formed of a laminated film of silicon oxide film 5a,
silicon nitride film 5b and silicon oxide film 5c and silicon oxide film 7a. In the present
embodiment, as apparent from the graph of FIG. 22, no shift was observed in the capacitancevoltage curve within the observed time (ie, the voltage shift Vsf was almost zero). On the other
hand, when only the silicon oxide films 105a and 107a are used as the insulating film between
the upper electrode wiring M1 (upper electrode M1E) and the lower electrode wiring M0 (lower
electrode M0E) as in the first comparative example, As also shown in the graph of FIG. 22, a
slight shift was seen in the capacitance-voltage curve. On the other hand, when only silicon
nitride films 105b and 107b are used as the insulating film between upper electrode wiring M1
(upper electrode M1E) and lower electrode wiring M0 (lower electrode M0E) as in the second
comparative example, As also shown in the 22 graph, a large voltage shift was observed in the
capacitance-voltage curve. The occurrence of a voltage shift in the capacitance-voltage curve
means that the transmission / reception sensitivity decreases when the CMUT cell is repeatedly
operated.
[0100]
Since a large number of charge traps exist in the silicon nitride film, the structure of the CMUT
04-05-2019
29
cell is the electrode (here, the lower electrode M0E or the upper electrode M1E) and the silicon
nitride film (here, the silicon nitride film) as in the second comparative example. In the structure
in which 105b and 107b) are in direct contact, a hole current flows and charge is trapped in the
trap of the silicon nitride film, and as a result, it is considered that the capacitance-voltage curve
shifts. As a result, as shown in the graph of FIG. 22, a large voltage shift occurs in the
capacitance-voltage curve in the second comparative example.
[0101]
On the other hand, in the case where the silicon nitride film 5b is sandwiched between the silicon
oxide film 5a and the silicon oxide film 5c to form a stacked structure as in the present
embodiment, the silicon nitride film 5b serves as the upper electrode M1E (upper electrode
wiring M1 And the lower electrode M0E (lower electrode wiring M0), and the hole current can be
suppressed. Therefore, it is considered possible to suppress or prevent the capacity shift due to
the charge accumulation in the insulating film due to the leak current. Therefore, in the present
embodiment, even if a drive voltage during actual operation is applied for a long time between
the upper electrode M1E (upper electrode wiring M1) and the lower electrode M0E (lower
electrode wiring M0), the voltage shifts in the capacitance-voltage curve. Can be suppressed or
prevented, and transmission and reception sensitivity does not change even if the CMUT cell is
repeatedly operated. Thereby, it is possible to suppress or prevent the fluctuation of the
transmission / reception sensitivity during the repetitive operation of the CMUT cell. Therefore,
the performance of the semiconductor chip 1 provided with the CMUT cell array can be
improved.
[0102]
Next, a case where the semiconductor device (semiconductor chip 1) of the present embodiment
is applied to, for example, an ultrasonic echo diagnostic apparatus will be described.
[0103]
An ultrasonic echo diagnostic apparatus is a medical diagnostic apparatus that uses ultrasound
transmission and makes it possible to visualize the inside of a living body, which can not be seen
from the outside, in real time using ultrasound that exceeds the audible sound area. is there.
The probe (probe) of this ultrasonic echo diagnostic apparatus is shown in FIG.
04-05-2019
30
[0104]
The probe 30 is a transmission / reception unit of ultrasonic waves. As shown in FIG. 24, the
semiconductor chip 1 is attached to the tip end surface of the probe case 30a forming the probe
30 with its first main surface (the surface on which the plurality of transducers 20 are formed)
directed to the outside. ing. Further, an acoustic lens 30 b is attached to the first main surface
side of the semiconductor chip 1.
[0105]
In ultrasonic diagnosis, after the tip of the probe 30 (on the side of the acoustic lens 30b) is
applied to the body surface (body surface), the probe is scanned while being gradually shifted by
a minute position. At this time, an ultrasonic pulse of several MHz is transmitted from the probe
30 applied to the body surface into the living body, and a reflected wave (echo or echo) from a
tissue boundary different in acoustic impedance is received. By this, it is possible to obtain a
tomogram of a living tissue and obtain information on an object. The distance information of the
reflector can be obtained by the time interval from the transmission of ultrasonic waves to the
reception of ultrasonic waves. Also, the level or contour of the reflected wave provides
information about the presence or quality of the reflector.
[0106]
The performance and reliability of the probe 30 can be improved by using the semiconductor
chip 1 of the present embodiment for the probe 30 of such an ultrasonic echo diagnostic
apparatus.
[0107]
Although the specific configuration of the semiconductor device of the present embodiment has
been described, the semiconductor devices of the present embodiment and the following second
to ninth embodiments face each other with the insulating film 5, the cavity VR and the insulating
film 7 interposed therebetween. Semiconductor device having a lower electrode M0E (lower
electrode wiring M0) and an upper electrode M1E (upper electrode wiring M1), which are
arranged as described above, and the insulating film 5 is formed on the lower electrode M0E
04-05-2019
31
(lower electrode wiring M0) An insulating film 7 is formed on the film 5, an upper electrode M1E
(upper electrode wiring M1) is formed on the insulating film 7, and a cavity VR is formed
between the insulating film 5 and the insulating film 7.
The insulating film 5 is at least in contact with the lower electrode M0E (lower electrode wiring
M0) with silicon oxide, and the insulating film 7 is at least in contact with the upper electrode
M1E (upper electrode wiring M1) with silicon oxide. At least one of insulating film 5 and
insulating film 7 is located between lower electrode M0E (lower electrode wire M0) and upper
electrode M1E (upper electrode wire M1), and also lower electrode M0E (lower electrode wire
M0) is upper electrode M1E. A silicon nitride layer portion not in contact with (upper electrode
wiring M1) is included. The silicon nitride layer portion corresponds to the silicon nitride film 5b
of the present embodiment and the silicon nitride films 5e, 7b and 7e of the embodiments
described later.
[0108]
Since at least one of insulating film 5 and insulating film 7 includes a silicon nitride layer portion
located between lower electrode M0E (lower electrode wiring M0) and upper electrode M1E
(upper electrode wiring M1), between the upper and lower electrodes The silicon nitride layer
portion intervenes, and the conduction mechanism of the insulating films 5 and 7 between the
upper electrode M1E (upper electrode wiring M1) and the lower electrode M0E (lower electrode
wiring M0) is mainly of the pool-Frenkel type. For this reason, as described above, the electric
field concentration portion does not receive the influence of the electric field concentration in the
portion corresponding to the upper surface end portion 121 of the lower electrode wiring M0
and the step portion 123 of the upper electrode wiring M1. It is possible to suppress or prevent
the occurrence of a leakage current or a dielectric breakdown between upper and lower
electrodes along a path (path corresponding to the paths 122 and 124) starting and ending at a
portion corresponding to 121 and the step portion 123). . Thereby, the withstand voltage
between the upper electrode M1E (upper electrode wiring M1) and the lower electrode M0E
(lower electrode wiring M0) can be improved. Therefore, the performance of the semiconductor
device can be improved, and the manufacturing yield can be improved.
[0109]
The portion of the insulating film 5 in contact with the lower electrode M0E (lower electrode
wiring M0) and the portion in contact with the upper electrode M1E of the insulating film 7
04-05-2019
32
(upper electrode wiring M1) are made of silicon oxide, and the insulating films 5 and 7 include
Since the silicon nitride layer portion is not in contact with either lower electrode M0E or upper
electrode M1E (upper electrode wiring M1), as described above, charge accumulation is
suppressed or suppressed in the silicon nitride layer portion, or It can prevent. Therefore, even if
a voltage is applied between upper electrode M1E and lower electrode M0E for a long time,
charge can be suppressed or prevented from being accumulated in the silicon nitride layer
portion included in insulating films 5 and 7, and to the silicon nitride layer portion It is possible
to suppress or prevent the characteristic of the capacitive element (vibrator) formed by the lower
electrode M0E, the insulating film 5, the cavity VR, the insulating film 7 and the upper electrode
M1E from fluctuating due to the charge accumulation. Therefore, the performance of the
semiconductor device can be improved.
[0110]
Therefore, it is possible to achieve both the improvement of the inter-electrode dielectric
breakdown voltage of the ultrasonic transducer and the suppression of the fluctuation of the
transmission / reception sensitivity due to the charge accumulation of the insulating film.
[0111]
The portion of the insulating film 5 in contact with the lower electrode M0E (lower electrode
wiring M0) and the portion in contact with the upper electrode M1E of the insulating film 7
(upper electrode wiring M1) are made of silicon oxide, and the insulating film 5 and the
insulating film In order to easily and properly realize a structure including a silicon nitride layer
portion which is not in contact with at least one of the lower electrode M0E (lower electrode
wiring M0) and the upper electrode M1E (upper electrode wiring M1), The film structure of the
insulating films 5 and 7 may be configured as follows.
[0112]
That is, the insulating film 5 is formed on the first silicon oxide film (silicon oxide films 5a and 5d
corresponding thereto) in contact with the lower electrode M0E (lower electrode wiring M0) and
the first silicon oxide film. A second silicon oxide film (silicon oxide film (silicon oxide film) is
formed of a laminated film including a silicon nitride film (silicon nitride films 5b and 5e
correspond thereto) and the insulating film 7 is in contact with the upper electrode M1E (upper
electrode wiring M1) The films 7a, 7c and 7f may be composed of a single film or a laminated
film including them.
04-05-2019
33
Alternatively, insulating film 5 is formed of a single film or a laminated film including a first
silicon oxide film (silicon oxide films 5a, 5d, 5f corresponding thereto) in contact with lower
electrode M0E (lower electrode interconnection M0), and The insulating film 7 is a second silicon
oxide film (silicon oxide films 7c and 7f corresponding thereto) in contact with the upper
electrode M1E (upper electrode wiring M1), and a nitride formed under the second silicon oxide
film. It may be configured by a laminated film including a silicon film (silicon nitride films 7 b
and 7 e correspond thereto).
[0113]
In the present embodiment, insulating film 5 is formed of a stacked film of silicon oxide film 5a,
silicon nitride film 5b and silicon oxide film 5c stacked in order from the lower side (lower
electrode M0E side), and insulating film 7 is oxidized Although the single film (single layer) of the
silicon film 7a is formed, another embodiment of the film structure of the insulating films 5 and
7 will be described in the following second to eighth embodiments.
The semiconductor devices of the following second to eighth embodiments have the same
structure as the semiconductor device of the present embodiment except for the film structures
of the insulating films 5 and 7.
[0114]
Second Embodiment FIGS. 25 and 26 are main-portion cross-sectional views of a semiconductor
device of the present embodiment, and correspond to FIGS. 5 and 6 of the first embodiment,
respectively.
[0115]
In the first embodiment, as shown in FIGS. 5 and 6, insulating film 5 is formed of a laminated film
of silicon oxide film 5a, silicon nitride film 5b and silicon oxide film 5c, and insulating film 7 is
silicon oxide. It was constituted by a single film (single layer) of the film 7a.
On the other hand, in the present embodiment, as shown in FIGS. 25 and 26, insulating film 5 is a
stack of silicon oxide film 5a, silicon nitride film 5b and silicon oxide film 5c as in the first
embodiment. In contrast to the first embodiment described above, the insulating film 7 is
04-05-2019
34
composed of a film, and is composed of a laminated film of a silicon nitride film 7 b and a silicon
oxide film 7 c sequentially stacked from the bottom (the insulating film 5 side). There is. Except
for this point, the structure of the semiconductor device of the present embodiment is the same
as that of the first embodiment, and thus the description thereof is omitted here.
[0116]
FIG. 27 is a cross-sectional view of essential parts in the process of manufacturing a
semiconductor device in the present embodiment, and corresponds to FIG. 13 in the first
embodiment.
[0117]
After the structure of FIG. 12 is obtained in the same manner as in the first embodiment, in the
present embodiment, as shown in FIG. 27, over the entire first main surface 1Sa of the
semiconductor substrate 1S (ie insulation Silicon nitride film 7b is formed (deposited) on the film
5 by plasma CVD or the like so as to cover the surface of the sacrificial film pattern 6, and the
silicon oxide film 7c is formed on the silicon nitride film 7b by plasma CVD or the like Form
(deposit) using
Thus, the insulating film 7 formed of a laminated film of the silicon nitride film 7 b and the
silicon oxide film 7 c is formed. The film thickness (deposited film thickness) of the silicon nitride
film 7b can be, for example, about 265 nm, and the film thickness (deposited film thickness) of
the silicon oxide film 7c can be, for example, about 50 nm.
[0118]
Then, the conductor film 8 for forming the upper electrode wiring M1 (upper electrode M1E) is
formed on the insulating film 7 formed of the laminated film of the silicon nitride film 7b and the
silicon oxide film 7c in the same manner as the first embodiment. The steps after the step of
forming the conductor film 8 are the same as those in the first embodiment, and thus the
description thereof is omitted here.
[0119]
Thus, as shown in FIGS. 25 and 26, a semiconductor device similar to that of the first
04-05-2019
35
embodiment can be obtained except that a laminated film of a silicon nitride film 7b and a silicon
oxide film 7c is used as the insulating film 7. .
[0120]
In the present embodiment, insulating films 5 and 7 include silicon nitride films 5b and 7b
located between lower electrode M0E (lower electrode interconnection M0) and upper electrode
M1E (upper electrode interconnection M1). The conduction mechanism of the insulating films 5
and 7 between the upper and lower electrodes is a pool-frenkel type, and the upper electrode
M1E (upper electrode wiring M1) and lower electrode M0E (lower electrode wiring M0) as
described in the first embodiment. Between them can be improved.
Therefore, the performance of the semiconductor device can be improved, and the manufacturing
yield can be improved.
[0121]
Further, in the present embodiment, the insulating film 7 is a laminated film of the silicon nitride
film 7 b and the silicon oxide film 7 c, so that the single-layer silicon oxide film 7 a is used as the
insulating film 7 as in the first embodiment. Compared to the case where the semiconductor
device is manufactured, the withstand voltage between the upper electrode M1E (upper electrode
wiring M1) and the lower electrode M0E (lower electrode wiring M0) can be further improved,
and the manufacturing yield of the semiconductor device can be further improved. This is
because the conduction mechanism of the insulating films 5 and 7 becomes closer to the poolFrenkel type by introducing the silicon nitride film 7b also to the insulating film 7 between the
cavity VR and the upper electrode wiring M1, and the lower electrode wiring M0. This is because
the influence of the electric field concentration at the step portion 123 of the upper surface end
portion 121 and the lower surface of the upper electrode wiring M1 is further alleviated.
[0122]
Further, in the present embodiment, the lowermost layer portion of the insulating film 5 is the
silicon oxide film 5a, and the uppermost layer portion of the insulating film 7 is the silicon oxide
film 7c, so that the lower electrode M0E of the insulating film 5 (lower electrode wiring The
04-05-2019
36
portion in contact with M0) and the portion in contact with the upper electrode M1E (upper
electrode wiring M1) of the insulating film 7 become silicon oxide films 5a and 7c, and the silicon
nitride films 5b and 7b included in the insulating films 5 and 7 are lower electrodes M0E and It
is not in contact with either of the upper electrodes M1E. Thus, as described in the first
embodiment, the charge accumulation in the silicon nitride films 5b and 7b included in the
insulating films 5 and 7 can be suppressed or prevented, and the charge accumulation in the
silicon nitride films 5b and 7b can be prevented. It is possible to suppress or prevent the
characteristic of the capacitive element (vibrator) formed by the lower electrode M0E, the
insulating film 5, the cavity VR, the insulating film 7 and the upper electrode M1E from
fluctuating. Therefore, the performance of the semiconductor device can be improved.
[0123]
Therefore, it is possible to achieve both the improvement of the inter-electrode dielectric
breakdown voltage of the ultrasonic transducer and the suppression of the fluctuation of the
transmission / reception sensitivity due to the charge accumulation of the insulating film.
[0124]
Further, in the present embodiment, the uppermost layer portion of the insulating film 5 is
formed of silicon oxide (here, the silicon oxide film 5c).
The sacrificial film pattern 6 is formed by patterning a sacrificial film formed on the entire
surface of the insulating film 5, but when patterning the sacrificial film, the uppermost layer
portion of the underlying insulating film 5 is also etched by overetching. There is a possibility.
However, if at least the uppermost layer portion of the insulating film 5 is formed of silicon oxide
(in this case, the silicon nitride layer portion is provided in the region other than the uppermost
layer portion of the insulating film 5 or in the insulating film 7), the insulating film Even if the
silicon oxide in the uppermost layer portion 5 is etched to some extent, it is possible to prevent
the silicon nitride layer portion introduced to the insulating films 5 and 7 from being etched in
order to improve the withstand voltage. Therefore, a silicon nitride layer portion (silicon nitride
films 5b, 5e, 7b, and 7e in this embodiment and other embodiments) having the same thickness
as the film thickness at the time of film formation is introduced into insulating films 5 and 7.
Thus, the withstand voltage between the upper electrode M1E (upper electrode wiring M1) and
the lower electrode M0E (lower electrode wiring M0) can be more appropriately improved. As
described above, at least the uppermost layer portion of the insulating film 5 is formed of silicon
oxide in the first embodiment, the second embodiment, the third embodiment described below,
the fifth embodiment described below, and the following embodiments. This is the eighth
04-05-2019
37
embodiment and can obtain the effects as described above.
[0125]
Third Embodiment FIGS. 28 and 29 are main-portion cross-sectional views of a semiconductor
device of the present embodiment, and correspond to FIGS. 5 and 6 of the first embodiment,
respectively.
[0126]
In the first embodiment, as shown in FIGS. 5 and 6, insulating film 5 is formed of a laminated film
of silicon oxide film 5a, silicon nitride film 5b and silicon oxide film 5c, and insulating film 7 is
silicon oxide. It was constituted by a single film (single layer) of the film 7a.
On the other hand, in the present embodiment, as shown in FIGS. 28 and 29, insulating film 5 is a
stack of silicon oxide film 5a, silicon nitride film 5b and silicon oxide film 5c as in the first
embodiment. Although the insulating film 7 is formed of a film, unlike the first embodiment, the
insulating film 7 is a stack of a silicon oxide film 7 d, a silicon nitride film 7 e, and a silicon oxide
film 7 f sequentially stacked from the bottom (the insulating film 5 side). It is composed of a
membrane. Except for this point, the structure of the semiconductor device of the present
embodiment is the same as that of the first embodiment, and thus the description thereof is
omitted here.
[0127]
FIG. 30 is a cross-sectional view of the essential part in the manufacturing process of the
semiconductor device of the present embodiment, and corresponds to FIG. 13 of the first
embodiment.
[0128]
After the structure of FIG. 12 is obtained in the same manner as in the first embodiment, in the
present embodiment, as shown in FIG. 30, over the entire first surface 1Sa of the semiconductor
substrate 1S (ie insulation Silicon oxide film 7d is formed (deposited) on the film 5 by plasma
CVD or the like so as to cover the surface of the sacrificial film pattern 6, and the silicon nitride
film 7e is formed on the silicon oxide film 7d by plasma CVD or the like The silicon oxide film 7 f
04-05-2019
38
is formed (deposited) on the silicon nitride film 7 e by plasma CVD or the like.
Thereby, the insulating film 7 formed of a laminated film of the silicon oxide film 7 d, the silicon
nitride film 7 e, and the silicon oxide film 7 f is formed. The film thickness (deposited film
thickness) of the silicon oxide film 7d is about 50 nm, the film thickness (deposited film
thickness) of the silicon nitride film 7e is about 175 nm, and the film thickness (deposited film
thickness) of the silicon oxide film 7f is about 50 nm It can be done.
[0129]
Then, on insulating film 7 formed of a laminated film of silicon oxide film 7d, silicon nitride film
7e and silicon oxide film 7f, a conductor film for forming upper electrode wiring M1 (upper
electrode M1E) as in the first embodiment. Form 8 The steps after the step of forming the
conductor film 8 are the same as those in the first embodiment, and thus the description thereof
is omitted here.
[0130]
Thus, as shown in FIGS. 28 and 29, a semiconductor similar to that of the first embodiment
except that a laminated film of silicon oxide film 7 d, silicon nitride film 7 e and silicon oxide film
7 f is used as insulating film 7. The device can be obtained.
[0131]
In the present embodiment, insulating films 5 and 7 include silicon nitride films 5b and 7e
located between lower electrode M0E (lower electrode interconnection M0) and upper electrode
M1E (upper electrode interconnection M1). The conduction mechanism of the insulating films 5
and 7 between the upper and lower electrodes is a pool-frenkel type, and the upper electrode
M1E (upper electrode wiring M1) and lower electrode M0E (lower electrode wiring M0) as
described in the first embodiment. Between them can be improved.
Therefore, the performance of the semiconductor device can be improved, and the manufacturing
yield can be improved.
04-05-2019
39
[0132]
Further, in the present embodiment, the insulating film 7 is a laminated film of the silicon oxide
film 7 d, the silicon nitride film 7 e, and the silicon oxide film 7 f, so that the insulating film 7 has
a single layer as in the first embodiment. The upper electrode M1E (upper electrode wiring M1)
compared to the case where the silicon oxide film 7a is used or the laminated film of the silicon
nitride film 7b and the silicon oxide film 7c is used as the insulating film 7 as in the second
embodiment. The insulation breakdown voltage between lower electrode M0E (lower electrode
wiring M0) can be further improved, and the manufacturing yield of the semiconductor device
can be further improved.
[0133]
Further, in the present embodiment, the lowermost layer portion of the insulating film 5 is the
silicon oxide film 5a, and the uppermost layer portion of the insulating film 7 is the silicon oxide
film 7f, so that the lower electrode M0E of the insulating film 5 (lower electrode wiring The
portion in contact with M0) and the portion in contact with the upper electrode M1E (upper
electrode wiring M1) of the insulating film 7 become the silicon oxide films 5a and 7f, and the
silicon nitride films 5b and 7e included in the insulating films 5 and 7 are the lower electrode
M0E and It is not in contact with either of the upper electrodes M1E.
Thereby, as described in the first embodiment, the charge accumulation in the silicon nitride
films 5b and 7e included in the insulating films 5 and 7 can be suppressed or prevented, and the
charge accumulation on the silicon nitride films 5b and 7e is achieved. It is possible to suppress
or prevent the characteristic of the capacitive element (vibrator) formed by the lower electrode
M0E, the insulating film 5, the cavity VR, the insulating film 7 and the upper electrode M1E from
fluctuating. Therefore, the performance of the semiconductor device can be improved.
[0134]
Therefore, it is possible to achieve both the improvement of the inter-electrode dielectric
breakdown voltage of the ultrasonic transducer and the suppression of the fluctuation of the
transmission / reception sensitivity due to the charge accumulation of the insulating film.
[0135]
Further, in the present embodiment, as shown in FIG. 30, the sacrificial film pattern 6 for forming
04-05-2019
40
the cavity VR is surrounded by the silicon oxide portion (here, the silicon oxide films 5c and 7d).
When etching the sacrificial film pattern 6 through the hole 10 to form the cavity VR as shown in
FIG. 17 above, the etching selectivity is increased (the insulating film around the sacrificial film
pattern 6 is prevented from being etched as much as possible). Is desirable. When the sacrificial
film pattern 6 is an amorphous silicon film, it is easier to increase the etching selectivity of the
sacrificial film pattern 6 if silicon oxide is used rather than silicon nitride around the sacrificial
film pattern 6 (sacrificial film The insulating film surrounding the pattern 6 is difficult to etch),
and the shape of the hollow portion VR tends to be stable. Therefore, in the manufactured
semiconductor device (semiconductor chip 1), if the cavity VR is in a state of being surrounded
by silicon oxide (silicon oxide portion), amorphous silicon is used as the sacrificial film pattern 6
for forming the cavity VR. A film or the like can be used, and the range of choices of the material
of the sacrificial film pattern 6 for forming the cavity VR can be expanded. As described above,
the cavity portion VR is surrounded by silicon oxide (silicon oxide portion) in the first
embodiment, the third embodiment, and the following eighth embodiment, as described above.
Effect can be obtained.
[0136]
Fourth Embodiment FIGS. 31 and 32 are main-portion cross-sectional views of a semiconductor
device of the present embodiment, and correspond to FIGS. 5 and 6 of the first embodiment,
respectively.
[0137]
In the first embodiment, as shown in FIGS. 5 and 6, insulating film 5 is formed of a laminated film
of silicon oxide film 5a, silicon nitride film 5b and silicon oxide film 5c, and insulating film 7 is
silicon oxide. It was constituted by a single film (single layer) of the film 7a.
On the other hand, in the present embodiment, as shown in FIGS. 31 and 32, the insulating film 7
is formed of a single film (single layer) of the silicon oxide film 7a as in the first embodiment.
Unlike the first embodiment, the insulating film 5 is formed of a laminated film of a silicon oxide
film 5d and a silicon nitride film 5e sequentially stacked from the lower side (lower electrode
M0E side). Except for this point, the structure of the semiconductor device of the present
embodiment is the same as that of the first embodiment, and thus the description thereof is
omitted here.
04-05-2019
41
[0138]
33 and 34 are main-portion cross-sectional views of the semiconductor device in the present
embodiment during the manufacturing process thereof, which correspond to FIGS. 11 and 13 in
the first embodiment, respectively.
[0139]
After the structure of FIG. 10 is obtained in the same manner as in the first embodiment, in the
present embodiment, as shown in FIG. 33, over the entire first surface 1Sa of the semiconductor
substrate 1S (ie, the lower portion Silicon oxide film 5d is formed (deposited) on the upper
surface of insulating film 4a filling the space between electrode interconnection M0 and lower
electrode interconnection M0 by plasma CVD or the like, and silicon nitride film 5e is plasmadeposited on silicon oxide film 5d. It is formed (deposited) using a CVD method or the like.
Thereby, the insulating film 5 formed of a laminated film of the silicon oxide film 5d and the
silicon nitride film 5e is formed. The film thickness (deposited film thickness) of the silicon oxide
film 5d can be, for example, about 50 nm, and the film thickness (deposited film thickness) of the
silicon nitride film 5e can be, for example, about 265 nm.
[0140]
After the formation of the insulating film 5, the same steps as those in the first embodiment are
performed. That is, as shown in FIG. 34, the sacrificial film pattern 6 is formed on the insulating
film 5 formed of the laminated film of the silicon oxide film 5d and the silicon nitride film 5e as
in the first embodiment, and then the insulating film is formed. An insulating film 7 made of a
silicon oxide film 7 a is formed on the surface 5 to cover the sacrificial film pattern 6. Then, on
the insulating film 7 made of the silicon oxide film 7a, the conductor film 8 for forming the upper
electrode wiring M1 (upper electrode M1E) is formed. The subsequent steps are the same as in
the first embodiment, and thus the description thereof is omitted here.
[0141]
Thus, as shown in FIGS. 31 and 32, a semiconductor device similar to that of the first
embodiment can be obtained except that a laminated film of silicon oxide film 5 d and silicon
nitride film 5 e is used as insulating film 5. it can.
04-05-2019
42
[0142]
In the present embodiment, insulating films 5 and 7 include silicon nitride film 5e located
between lower electrode M0E (lower electrode interconnection M0) and upper electrode M1E
(upper electrode interconnection M1), whereby upper and lower The conduction mechanism of
the insulating films 5 and 7 between the electrodes becomes a pool-Frenkel type, and as
described in the first embodiment, between the upper electrode M1E (upper electrode wiring
M1) and lower electrode M0E (lower electrode wiring M0) The withstand voltage can be
improved.
Therefore, the performance of the semiconductor device can be improved, and the manufacturing
yield can be improved.
[0143]
Further, in the present embodiment, the lowermost portion of the insulating film 5 is the silicon
oxide film 5d, and the insulating film 7 is the silicon oxide film 7a, so that the lower electrode
M0E (lower electrode wiring M0) of the insulating film 5 is in contact. The silicon oxide films 5d
and 7a are the portions and portions of the insulating film 7 in contact with the upper electrode
M1E (upper electrode wiring M1), and the silicon nitride film 5e included in the insulating films
5 and 7 is used as either the lower electrode M0E or the upper electrode M1E. It is supposed not
to touch either. Thereby, as described in the first embodiment, accumulation of charges in the
silicon nitride film 5e included in the insulating films 5 and 7 can be suppressed or prevented,
and charge accumulation in the silicon nitride film 5e is caused. It is possible to suppress or
prevent the characteristic of the capacitive element (vibrator) formed by the lower electrode
M0E, the insulating film 5, the cavity VR, the insulating film 7 and the upper electrode M1E from
fluctuating. Therefore, the performance of the semiconductor device can be improved.
[0144]
Therefore, it is possible to achieve both the improvement of the inter-electrode dielectric
breakdown voltage of the ultrasonic transducer and the suppression of the fluctuation of the
transmission / reception sensitivity due to the charge accumulation of the insulating film.
04-05-2019
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[0145]
Fifth Embodiment FIGS. 35 and 36 are main-portion cross-sectional views of a semiconductor
device of the present embodiment, and correspond to FIG. 5 and FIG. 6 of the first embodiment,
respectively.
[0146]
In the first embodiment, as shown in FIGS. 5 and 6, insulating film 5 is formed of a laminated film
of silicon oxide film 5a, silicon nitride film 5b and silicon oxide film 5c, and insulating film 7 is
silicon oxide. It was constituted by a single film (single layer) of the film 7a.
On the other hand, in the present embodiment, as shown in FIGS. 35 and 36, the insulating film 5
is composed of a single film (single layer) of the silicon oxide film 5 f, unlike the first
embodiment. Insulating film 7 is different from the first embodiment (and in the same manner as
the second embodiment) from the laminated film of the silicon nitride film 7 b and the silicon
oxide film 7 c sequentially laminated from the lower side (the insulating film 5 side). It is
configured.
Except for this point, the structure of the semiconductor device of the present embodiment is the
same as that of the first embodiment, and thus the description thereof is omitted here.
[0147]
FIGS. 37 and 38 are main-portion cross-sectional views of the semiconductor device in the
present embodiment during the manufacturing process thereof, which correspond to FIGS. 11
and 13 in the first embodiment, respectively.
[0148]
After the structure of FIG. 10 is obtained in the same manner as in the first embodiment, in the
present embodiment, as shown in FIG. 37, over the entire first surface 1Sa of the semiconductor
substrate 1S (ie, the lower portion Silicon oxide film 5f is formed (deposited) using plasma CVD
or the like on the upper surface of insulating film 4a filling the space between electrode
interconnection M0 and lower electrode interconnection M0.
04-05-2019
44
Thus, the insulating film 5 formed of a single film (single layer) of the silicon oxide film 5 f is
formed. The film thickness (deposited film thickness) of the silicon oxide film 5 f can be, for
example, about 200 nm.
[0149]
After the formation of the insulating film 5, the process similar to that of the first embodiment is
performed just before the formation of the insulating film 7. That is, as shown in FIG. 38, the
sacrificial film pattern 6 is formed on the insulating film 5 made of the silicon oxide film 5f in the
same manner as the first embodiment.
[0150]
Then, in the present embodiment, as in the second embodiment, the surface of the sacrificial film
pattern 6 is covered on the entire surface on the first main surface 1Sa of the semiconductor
substrate 1S (that is, on the insulating film 5), A silicon nitride film 7b is formed (deposited) by
plasma CVD or the like, and a silicon oxide film 7c is formed (deposited) on the silicon nitride
film 7b by plasma CVD or the like. Thus, the insulating film 7 formed of a laminated film of the
silicon nitride film 7 b and the silicon oxide film 7 c is formed. The film thickness (deposited film
thickness) of the silicon nitride film 7b can be, for example, about 265 nm, and the film thickness
(deposited film thickness) of the silicon oxide film 7c can be, for example, about 50 nm.
[0151]
Then, the conductor film 8 for forming the upper electrode wiring M1 (upper electrode M1E) is
formed on the insulating film 7 formed of the laminated film of the silicon nitride film 7b and the
silicon oxide film 7c in the same manner as the first embodiment. The steps after the step of
forming the conductor film 8 are the same as those in the first embodiment, and thus the
description thereof is omitted here.
[0152]
Thus, as shown in FIGS. 35 and 36, a single film (single layer) of silicon oxide film 5f is used as
insulating film 5, and a laminated film of silicon nitride film 7b and silicon oxide film 7c is used
04-05-2019
45
as insulating film 7. It is possible to obtain the same semiconductor device as that of the first
embodiment except that it is used.
[0153]
In the present embodiment, insulating films 5 and 7 include silicon nitride film 7 b located
between lower electrode M 0 E (lower electrode interconnection M 0) and upper electrode M 1 E
(upper electrode interconnection M 1), thereby forming upper and lower The conduction
mechanism of the insulating films 5 and 7 between the electrodes becomes a pool-Frenkel type,
and as described in the first embodiment, between the upper electrode M1E (upper electrode
wiring M1) and lower electrode M0E (lower electrode wiring M0) The withstand voltage can be
improved.
Therefore, the performance of the semiconductor device can be improved, and the manufacturing
yield can be improved.
[0154]
Further, in the present embodiment, the insulating film 5 is the silicon oxide film 5 f, and the
uppermost layer portion of the insulating film 7 is the silicon oxide film 7 c, thereby being in
contact with the lower electrode M0E (lower electrode wiring M0) of the insulating film 5. The
silicon oxide films 5f and 7c are the portion and the portion of the insulating film 7 in contact
with the upper electrode M1E (upper electrode wiring M1), and the silicon nitride film 7b
included in the insulating films 5 and 7 is used as either the lower electrode M0E or the upper
electrode M1E. It is supposed not to touch either. Thereby, as described in the first embodiment,
accumulation of charges in the silicon nitride film 7b included in the insulating films 5 and 7 can
be suppressed or prevented, and charge accumulation in the silicon nitride film 7b is caused. It is
possible to suppress or prevent the characteristic of the capacitive element (vibrator) formed by
the lower electrode M0E, the insulating film 5, the cavity VR, the insulating film 7 and the upper
electrode M1E from fluctuating. Therefore, the performance of the semiconductor device can be
improved.
[0155]
Therefore, it is possible to achieve both the improvement of the inter-electrode dielectric
breakdown voltage of the ultrasonic transducer and the suppression of the fluctuation of the
04-05-2019
46
transmission / reception sensitivity due to the charge accumulation of the insulating film.
[0156]
Sixth Embodiment FIGS. 39 and 40 are main-portion cross-sectional views of a semiconductor
device of the present embodiment, and correspond to FIGS. 5 and 6 of the first embodiment,
respectively.
[0157]
In the first embodiment, as shown in FIGS. 5 and 6, insulating film 5 is formed of a laminated film
of silicon oxide film 5a, silicon nitride film 5b and silicon oxide film 5c, and insulating film 7 is
silicon oxide. It was constituted by a single film (single layer) of the film 7a.
On the other hand, in the present embodiment, as shown in FIGS. 39 and 40, the insulating film 5
is different from the first embodiment (and similar to the fourth embodiment), lower (bottom
electrode The insulating film 7 is different from that of the first embodiment (and similar to the
second and fifth embodiments described above), and is formed of a stacked film of a silicon oxide
film 5d and a silicon nitride film 5e sequentially stacked from the M0E side). And a laminated
film of a silicon nitride film 7 b and a silicon oxide film 7 c laminated in order from the lower side
(the insulating film 5 side).
Except for this point, the structure of the semiconductor device of the present embodiment is the
same as that of the first embodiment, and thus the description thereof is omitted here.
[0158]
41 and 42 are main-portion cross-sectional views of the semiconductor device in the present
embodiment during the manufacturing process thereof, which correspond to FIGS. 11 and 13,
respectively, of the first embodiment.
[0159]
After the structure of FIG. 10 is obtained in the same manner as in the first embodiment, in the
present embodiment, as shown in FIG. 41, the first main portion of the semiconductor substrate
04-05-2019
47
1S is obtained, as in the fourth embodiment. A silicon oxide film 5d is formed (deposited) using
plasma CVD or the like over the entire surface 1Sa (that is, on the upper surface of insulating film
4a filling the space between lower electrode interconnection M0 and lower electrode
interconnection M0). A silicon nitride film 5e is formed (deposited) on the surface 5d by plasma
CVD or the like.
Thereby, the insulating film 5 formed of a laminated film of the silicon oxide film 5d and the
silicon nitride film 5e is formed. The film thickness (deposited film thickness) of the silicon oxide
film 5d can be, for example, about 50 nm, and the film thickness (deposited film thickness) of the
silicon nitride film 5e can be, for example, about 265 nm.
[0160]
After the formation of the insulating film 5, the process similar to that of the first embodiment is
performed just before the formation of the insulating film 7. That is, as shown in FIG. 42, the
sacrificial film pattern 6 is formed on the insulating film 5 formed of the laminated film of the
silicon oxide film 5d and the silicon nitride film 5e as in the first embodiment.
[0161]
Then, in the present embodiment, the surface of the sacrificial film pattern 6 is covered on the
entire surface on the first main surface 1Sa of the semiconductor substrate 1S (that is, on the
insulating film 5) as in the second and fifth embodiments. Then, a silicon nitride film 7b is
formed (deposited) by plasma CVD or the like, and a silicon oxide film 7c is formed (deposited)
on the silicon nitride film 7b by plasma CVD or the like. Thus, the insulating film 7 formed of a
laminated film of the silicon nitride film 7 b and the silicon oxide film 7 c is formed. The film
thickness (deposited film thickness) of the silicon nitride film 7b can be, for example, about 265
nm, and the film thickness (deposited film thickness) of the silicon oxide film 7c can be, for
example, about 50 nm.
[0162]
Then, conductive film 8 for forming upper electrode wiring M1 (upper electrode M1E) is formed
on insulating film 7 formed of a laminated film of a laminated film of silicon nitride film 7b and
04-05-2019
48
silicon oxide film 7c as in the first embodiment. Form. The steps after the step of forming the
conductor film 8 are the same as those in the first embodiment, and thus the description thereof
is omitted here.
[0163]
Thus, as shown in FIGS. 39 and 40, a laminated film of silicon oxide film 5d and silicon nitride
film 5e is used for insulating film 5, and a laminated film of silicon nitride film 7b and silicon
oxide film 7c is used for insulating film 7. The same semiconductor device as that of the abovedescribed first embodiment can be obtained except using.
[0164]
In the present embodiment, insulating films 5 and 7 include silicon nitride films 5e and 7b
located between lower electrode M0E (lower electrode interconnection M0) and upper electrode
M1E (upper electrode interconnection M1). The conduction mechanism of the insulating films 5
and 7 between the upper and lower electrodes is a pool-frenkel type, and the upper electrode
M1E (upper electrode wiring M1) and lower electrode M0E (lower electrode wiring M0) as
described in the first embodiment. Between them can be improved.
Therefore, the performance of the semiconductor device can be improved, and the manufacturing
yield can be improved.
[0165]
Further, in the present embodiment, since the insulating films 5 and 7 include the two layers of
silicon nitride films 5e and 7b, the conduction mechanism of the insulating films 5 and 7 is
greater than the case where the silicon nitride film is one layer. It becomes closer to the poolFrenkel type, and the withstand voltage between the upper electrode M1E (upper electrode
wiring M1) and the lower electrode M0E (lower electrode wiring M0) can be further improved,
and the manufacturing yield of the semiconductor device can be further improved.
[0166]
Further, in the present embodiment, the lowermost layer portion of the insulating film 5 is the
silicon oxide film 5d, and the uppermost layer portion of the insulating film 7 is the silicon oxide
04-05-2019
49
film 7c, so that the lower electrode M0E of the insulating film 5 (lower electrode wiring The
portions in contact with M0 and the portions in contact with the upper electrode M1E (upper
electrode wiring M1) of the insulating film 7 become silicon oxide films 5d and 7c, and the
silicon nitride films 5e and 7b included in the insulating films 5 and 7 are lower electrodes M0E
and It is not in contact with either of the upper electrodes M1E.
Thereby, as described in the first embodiment, the charge accumulation in the silicon nitride
films 5e and 7b included in the insulating films 5 and 7 can be suppressed or prevented, and the
charge accumulation in the silicon nitride films 5e and 7b is achieved. It is possible to suppress
or prevent the characteristic of the capacitive element (vibrator) formed by the lower electrode
M0E, the insulating film 5, the cavity VR, the insulating film 7 and the upper electrode M1E from
fluctuating. Therefore, the performance of the semiconductor device can be improved.
[0167]
Therefore, it is possible to achieve both the improvement of the inter-electrode dielectric
breakdown voltage of the ultrasonic transducer and the suppression of the fluctuation of the
transmission / reception sensitivity due to the charge accumulation of the insulating film.
[0168]
Seventh Embodiment FIGS. 43 and 44 are main-portion cross-sectional views of a semiconductor
device of the present embodiment, and correspond to FIGS. 5 and 6 of the first embodiment,
respectively.
[0169]
In the first embodiment, as shown in FIGS. 5 and 6, insulating film 5 is formed of a laminated film
of silicon oxide film 5a, silicon nitride film 5b and silicon oxide film 5c, and insulating film 7 is
silicon oxide. It was constituted by a single film (single layer) of the film 7a.
On the other hand, in the present embodiment, as shown in FIGS. 43 and 44, the insulating film 5
is different from the first embodiment (and similar to the fourth and sixth embodiments) and
lower ( The insulating film 7 is different from that of the first embodiment (and similar to the
third embodiment), and is formed of a laminated film of a silicon oxide film 5d and a silicon
nitride film 5e sequentially stacked from the lower electrode M0E side). And a laminated film of a
silicon oxide film 7d, a silicon nitride film 7e, and a silicon oxide film 7f, which are sequentially
04-05-2019
50
stacked from the lower side (the insulating film 5 side).
Except for this point, the structure of the semiconductor device of the present embodiment is the
same as that of the first embodiment, and thus the description thereof is omitted here.
[0170]
45 and 46 are main-portion cross-sectional views of the semiconductor device in the present
embodiment during the manufacturing process thereof, which correspond to FIGS. 11 and 13 in
the first embodiment, respectively.
[0171]
After the structure of FIG. 10 is obtained in the same manner as in the first embodiment, in the
present embodiment, as shown in FIG. 45, as in the fourth and sixth embodiments, as shown in
FIG. A silicon oxide film 5d is formed (deposited) using plasma CVD or the like on the entire
surface over one main surface 1Sa (ie, on the upper surface of insulating film 4a filling the space
between lower electrode interconnection M0 and lower electrode interconnection M0). A silicon
nitride film 5e is formed (deposited) on the silicon film 5d by plasma CVD or the like.
Thereby, the insulating film 5 formed of a laminated film of the silicon oxide film 5d and the
silicon nitride film 5e is formed. The film thickness (deposited film thickness) of the silicon oxide
film 5d can be, for example, about 50 nm, and the film thickness (deposited film thickness) of the
silicon nitride film 5e can be, for example, about 265 nm.
[0172]
After the formation of the insulating film 5, the process similar to that of the first embodiment is
performed just before the formation of the insulating film 7. That is, as shown in FIG. 46, the
sacrificial film pattern 6 is formed on the insulating film 5 formed of the laminated film of the
silicon oxide film 5d and the silicon nitride film 5e in the same manner as in the first
embodiment.
[0173]
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51
Then, in the present embodiment, as in the third embodiment, the surface of the sacrificial film
pattern 6 is covered on the entire surface of the first main surface 1Sa of the semiconductor
substrate 1S (that is, on the insulating film 5), A silicon oxide film 7d is formed (deposited) by
plasma CVD or the like, and a silicon nitride film 7e is formed (deposited) on the silicon oxide
film 7d by plasma CVD or the like, and silicon oxide is formed on the silicon nitride film 7e. The
film 7f is formed (deposited) using a plasma CVD method or the like. Thereby, the insulating film
7 formed of a laminated film of the silicon oxide film 7 d, the silicon nitride film 7 e, and the
silicon oxide film 7 f is formed. The film thickness (deposited film thickness) of the silicon oxide
film 7d is about 50 nm, the film thickness (deposited film thickness) of the silicon nitride film 7e
is about 175 nm, and the film thickness (deposited film thickness) of the silicon oxide film 7f is
about 50 nm It can be done.
[0174]
Then, on insulating film 7 formed of a laminated film of silicon oxide film 7d, silicon nitride film
7e and silicon oxide film 7f, a conductor film for forming upper electrode wiring M1 (upper
electrode M1E) as in the first embodiment. Form 8 The steps after the step of forming the
conductor film 8 are the same as those in the first embodiment, and thus the description thereof
is omitted here.
[0175]
Thus, as shown in FIGS. 43 and 44, a laminated film of silicon oxide film 5d and silicon nitride
film 5e is used for insulating film 5, and silicon oxide film 7d, silicon nitride film 7e and silicon
oxide are used for insulating film 7. A semiconductor device similar to that of the first
embodiment can be obtained except that the laminated film of the film 7f is used.
[0176]
In the present embodiment, insulating films 5 and 7 include silicon nitride films 5e and 7e
located between lower electrode M0E (lower electrode interconnection M0) and upper electrode
M1E (upper electrode interconnection M1). The conduction mechanism of the insulating films 5
and 7 between the upper and lower electrodes is a pool-frenkel type, and the upper electrode
M1E (upper electrode wiring M1) and lower electrode M0E (lower electrode wiring M0) as
described in the first embodiment. Between them can be improved.
04-05-2019
52
Therefore, the performance of the semiconductor device can be improved, and the manufacturing
yield can be improved.
[0177]
Further, in the present embodiment, since insulating films 5 and 7 include two layers of silicon
nitride films 5e and 7e, the conduction mechanism of insulating films 5 and 7 is more than that
in the case of one silicon nitride film. It becomes similar to the pool-Frenkel type, and further the
silicon oxide film 7d intervenes between the silicon nitride films 5e and 7e, whereby the
insulation between the upper electrode M1E (upper electrode wiring M1) and the lower electrode
M0E (lower electrode wiring M0) The breakdown voltage can be further improved, and the
manufacturing yield of the semiconductor device can be further improved.
[0178]
Further, in the present embodiment, the lowermost layer portion of the insulating film 5 is the
silicon oxide film 5d, and the uppermost layer portion of the insulating film 7 is the silicon oxide
film 7f, so that the lower electrode M0E of the insulating film 5 (lower electrode wiring The
portion in contact with M0) and the portion in contact with the upper electrode M1E (upper
electrode wiring M1) of the insulating film 7 become silicon oxide films 5d and 7f, and the silicon
nitride films 5e and 7e included in the insulating films 5 and 7 are lower electrodes M0E and It is
not in contact with either of the upper electrodes M1E.
Thereby, as described in the first embodiment, accumulation of charges in the silicon nitride
films 5e and 7e included in the insulating films 5 and 7 can be suppressed or prevented, and
charge accumulation on the silicon nitride films 5e and 7e It is possible to suppress or prevent
the characteristic of the capacitive element (vibrator) formed by the lower electrode M0E, the
insulating film 5, the cavity VR, the insulating film 7 and the upper electrode M1E from
fluctuating. Therefore, the performance of the semiconductor device can be improved.
[0179]
Therefore, it is possible to achieve both the improvement of the inter-electrode dielectric
breakdown voltage of the ultrasonic transducer and the suppression of the fluctuation of the
transmission / reception sensitivity due to the charge accumulation of the insulating film.
04-05-2019
53
[0180]
Eighth Embodiment FIGS. 47 and 48 are main-portion cross-sectional views of the semiconductor
device of the present embodiment, and correspond to FIGS. 5 and 6 of the first embodiment,
respectively.
[0181]
In the first embodiment, as shown in FIGS. 5 and 6, insulating film 5 is formed of a laminated film
of silicon oxide film 5a, silicon nitride film 5b and silicon oxide film 5c, and insulating film 7 is
silicon oxide. It was constituted by a single film (single layer) of the film 7a.
On the other hand, in the present embodiment, as shown in FIGS. 47 and 48, insulating film 5 is
different from the above-described first embodiment (and in the same manner as the abovementioned fifth embodiment), silicon oxide film 5f. The insulating film 7 is stacked in order from
the bottom (the insulating film 5 side), unlike the first embodiment (and in the same manner as
the third and seventh embodiments). It is formed of a laminated film of a silicon oxide film 7d, a
silicon nitride film 7e and a silicon oxide film 7f.
Except for this point, the structure of the semiconductor device of the present embodiment is the
same as that of the first embodiment, and thus the description thereof is omitted here.
[0182]
49 and 50 are main-portion cross-sectional views of the semiconductor device in the present
embodiment during the manufacturing process thereof, which correspond to FIGS. 11 and 13 in
the first embodiment, respectively.
[0183]
After the structure of FIG. 10 is obtained in the same manner as in the first embodiment, in the
present embodiment, as shown in FIG. 49, as in the fifth embodiment, the first main
semiconductor substrate 1S is obtained. A silicon oxide film 5f is formed (deposited) by plasma
CVD or the like on the entire surface (that is, on the upper surface of the insulating film 4a filling
the space between the lower electrode wiring M0 and the lower electrode wiring M0).
04-05-2019
54
Thus, the insulating film 5 formed of a single film (single layer) of the silicon oxide film 5 f is
formed. The film thickness (deposited film thickness) of the silicon oxide film 5 f can be, for
example, about 200 nm.
[0184]
After the formation of the insulating film 5, the process similar to that of the first embodiment is
performed just before the formation of the insulating film 7. That is, as shown in FIG. 50, the
sacrificial film pattern 6 is formed on the insulating film 5 made of the silicon oxide film 5f in the
same manner as the first embodiment.
[0185]
Then, in the present embodiment, the surface of the sacrificial film pattern 6 is covered on the
entire surface on the first main surface 1Sa of the semiconductor substrate 1S (that is, on the
insulating film 5) as in the third and seventh embodiments. Then, a silicon oxide film 7d is
formed (deposited) by plasma CVD or the like, and a silicon nitride film 7e is formed (deposited)
on the silicon oxide film 7d by plasma CVD or the like, and is formed on the silicon nitride film
7e. The silicon oxide film 7f is formed (deposited) by plasma CVD or the like. Thereby, the
insulating film 7 formed of a laminated film of the silicon oxide film 7 d, the silicon nitride film 7
e, and the silicon oxide film 7 f is formed. The film thickness (deposited film thickness) of the
silicon oxide film 7d is about 50 nm, the film thickness (deposited film thickness) of the silicon
nitride film 7e is about 175 nm, and the film thickness (deposited film thickness) of the silicon
oxide film 7f is about 50 nm It can be done.
[0186]
Then, on insulating film 7 formed of a laminated film of silicon oxide film 7d, silicon nitride film
7e and silicon oxide film 7f, a conductor film for forming upper electrode wiring M1 (upper
electrode M1E) as in the first embodiment. Form 8 The steps after the step of forming the
conductor film 8 are the same as those in the first embodiment, and thus the description thereof
is omitted here.
04-05-2019
55
[0187]
Thus, as shown in FIGS. 47 and 48, a single film (single layer) of silicon oxide film 5f is used as
insulating film 5, and silicon oxide film 7d, silicon nitride film 7e and silicon oxide film are used
as insulating film 7. A semiconductor device similar to that of the first embodiment can be
obtained except that the laminated film 7f is used.
[0188]
In the present embodiment, insulating films 5 and 7 include upper and lower silicon nitride films
7e located between lower electrode M0E (lower electrode interconnection M0) and upper
electrode M1E (upper electrode interconnection M1). The conduction mechanism of the
insulating films 5 and 7 between the electrodes becomes a pool-Frenkel type, and as described in
the first embodiment, between the upper electrode M1E (upper electrode wiring M1) and lower
electrode M0E (lower electrode wiring M0) The withstand voltage can be improved.
Therefore, the performance of the semiconductor device can be improved, and the manufacturing
yield can be improved.
[0189]
Further, in the present embodiment, the insulating film 5 is the silicon oxide film 5f, and the
uppermost layer portion of the insulating film 7 is the silicon oxide film 7f, so that the lower
electrode M0E (lower electrode wiring M0) of the insulating film 5 is in contact. The silicon oxide
films 5f and 7f are the portion and the portion of the insulating film 7 in contact with the upper
electrode M1E (upper electrode wiring M1), and the silicon nitride film 7e included in the
insulating films 5 and 7 is used as either the lower electrode M0E or the upper electrode M1E. It
is supposed not to touch either. Thereby, as described in the first embodiment, accumulation of
charges in the silicon nitride film 7e included in the insulating films 5 and 7 can be suppressed
or prevented, and charge accumulation in the silicon nitride film 7e is caused. It is possible to
suppress or prevent the characteristic of the capacitive element (vibrator) formed by the lower
electrode M0E, the insulating film 5, the cavity VR, the insulating film 7 and the upper electrode
M1E from fluctuating. Therefore, the performance of the semiconductor device can be improved.
[0190]
04-05-2019
56
Therefore, it is possible to achieve both the improvement of the inter-electrode dielectric
breakdown voltage of the ultrasonic transducer and the suppression of the fluctuation of the
transmission / reception sensitivity due to the charge accumulation of the insulating film.
[0191]
Ninth Embodiment FIGS. 51 and 52 are main-portion cross-sectional views of a semiconductor
device of the present embodiment, and correspond to FIGS. 5 and 6 of the first embodiment,
respectively.
[0192]
In the first embodiment described above, lower electrode M0E (lower electrode wiring M0),
insulating film 5, cavity VR, insulating film 7 and upper electrode M1E (upper electrode wiring
M1) on (main surface 1Sa of) semiconductor substrate 1S. The lower electrode M0E (lower
electrode wiring M0) is provided on the main surface 1Sa of the semiconductor substrate 1S with
the insulating film 2 interposed therebetween, and is formed of the patterned conductor film 3.
The
On the other hand, in the present embodiment, the one corresponding to the lower electrode
M0E (lower electrode wiring M0) is constituted by the n-type semiconductor region 41 formed in
the semiconductor substrate 1S.
[0193]
That is, in the present embodiment, as shown in FIGS. 51 and 52, an n-type semiconductor region
(impurity diffusion layer) 41 is formed in the surface layer portion in the semiconductor
substrate 1S.
The n-type semiconductor region 41 functions as the lower electrode M0E. Therefore, in the
present embodiment, the lower electrode M0E is formed of a part of the semiconductor substrate
1S (here, in the embodiment, the n-type semiconductor region 41). Then, in the present
embodiment, the portions corresponding to insulating film 2, conductor film 3 and insulating
film 4 (4a) of the first embodiment are not formed, and on the main surface of semiconductor
substrate 1S (ie, n (The cavity VR, the insulating film 7, the upper electrode wiring M1, and the
04-05-2019
57
insulating films 9, 11, 13) are formed on the insulating film 5 of the first embodiment and the
structure above the insulating film 5 of the first embodiment. There is. Except for this point, the
structure of the semiconductor device of the present embodiment is the same as that of the first
embodiment, and thus the description thereof is omitted here.
[0194]
53 and 54 are main-portion cross-sectional views of the semiconductor device in the present
embodiment during the manufacturing process thereof, which correspond to FIG. 11 and FIG. 13
of the first embodiment, respectively.
[0195]
In the present embodiment, after preparing the semiconductor substrate 1S, as shown in FIG. 53,
n-type impurities such as phosphorus (P) or arsenic (As) are ion-implanted into the surface layer
portion of the semiconductor substrate 1S. The n-type semiconductor region 41 is formed by the
like.
[0196]
Next, the insulating film 5 is formed on the entire main surface of the semiconductor substrate
1S, that is, on the semiconductor region 41 without forming the insulating film 2, the conductor
film 3 and the insulating film 4 (4a) accumulate.
Also in the present embodiment, as in the first embodiment, the insulating film 5 is formed of a
laminated film of the silicon oxide film 5a, the silicon nitride film 5b and the silicon oxide film 5c
in order from the bottom, and the same as the first embodiment. Can be formed.
[0197]
After the formation of the insulating film 5, the same steps as those in the first embodiment are
performed.
More specifically, as shown in FIG. 54, sacrificial film pattern 6 is formed on insulating film 5 in
the same manner as in the first embodiment, and the entire surface over semiconductor substrate
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58
1S over first main surface 1Sa (ie, insulating film). 5) to form (deposit) the insulating film 7 made
of the silicon oxide film 7a so as to cover the surface of the sacrificial film pattern 6 and to form
the upper electrode wiring M1 (upper electrode M1E) on the insulating film 7 The film 8 is
formed. The steps after the step of forming the conductor film 8 are the same as those in the first
embodiment, and thus the description thereof is omitted here.
[0198]
In the present embodiment, lower electrode M0E is formed of a part of semiconductor substrate
1S (in this embodiment, n-type semiconductor region 41), so the upper surface of lower electrode
M0E (n-type semiconductor region 41) is flat. Thus, no corner (pointed portion) such as the
upper surface end 121 shown in FIG. 19 is formed on the upper surface of the lower electrode
M0E (n-type semiconductor region 41). Therefore, in the present embodiment, a portion where
the electric field is concentrated hardly occurs in lower electrode M0E (n-type semiconductor
region 41), and leakage current and dielectric breakdown easily occur in the path corresponding
to path 122 in FIG. There is nothing to do. However, also in the present embodiment, as in the
first embodiment, on the lower surface of upper electrode M1E (upper electrode wiring M1), a
stepped portion (corner, stepped corner) 123a due to cavity VR (Corresponding to the step
portion 123), an electric field is concentrated on the step portion 123a, and a path (a path
corresponding to the path 124 shown in FIG. 19) having the step portion 123a as a starting point
or an end point Leakage current and dielectric breakdown are likely to occur. Therefore, even in
the case where the lower electrode M0E is formed of a part of the semiconductor substrate 1S (in
the present embodiment, the n-type semiconductor region 41) as in the present embodiment,
there are the same problems as in the first embodiment.
[0199]
In the present embodiment, the insulating films 5 and 7 include the silicon nitride film 5b located
between the lower electrode M0E (n-type semiconductor region 41) and the upper electrode
M1E (upper electrode wiring M1). The conduction mechanism of the insulating films 5 and 7
between the M1E (upper electrode wiring M1) and the lower electrode M0E (n-type
semiconductor region 41) is a pool-Frenkel type, and as described in the first embodiment, the
upper electrode M1E (upper The withstand voltage between the stepped portion 123a of the
upper electrode wiring M1) and the lower electrode M0E (n-type semiconductor region 41) can
be improved. Therefore, the performance of the semiconductor device can be improved, and the
manufacturing yield can be improved.
04-05-2019
59
[0200]
Further, in the present embodiment, the lowermost portion of the insulating film 5 is the silicon
oxide film 5a, and the insulating film 7 is the silicon oxide film 7a, so that the lower electrode
M0E (n-type semiconductor region 41) of the insulating film 5 is formed. The portions in contact
with and the portions in contact with the upper electrode M1E (upper electrode wiring M1) of
the insulating film 7 become the silicon oxide films 5a and 7a, and the silicon nitride film 5b
included in the insulating films 5 and 7 is the lower electrode M0E (n-type semiconductor region
41). And the upper electrode M1E. Thereby, as described in the first embodiment, accumulation
of charges in the silicon nitride film 5b included in the insulating films 5 and 7 can be
suppressed or prevented, and charge accumulation in the silicon nitride film 5b is caused. It is
possible to suppress or prevent the characteristic of the capacitive element (vibrator) formed by
the lower electrode M0E (n-type semiconductor region 41), the insulating film 5, the cavity VR,
the insulating film 7 and the upper electrode M1E from fluctuating. Therefore, the performance
of the semiconductor device can be improved.
[0201]
Therefore, it is possible to achieve both the improvement of the inter-electrode dielectric
breakdown voltage of the ultrasonic transducer and the suppression of the fluctuation of the
transmission / reception sensitivity due to the charge accumulation of the insulating film.
[0202]
Further, in the present embodiment, the n-type semiconductor region 41 is formed over the
entire CMUT region CA to be a common lower electrode M0E.
On the other hand, in the first to eighth embodiments, lower electrode interconnection M0 (lower
electrode M0E) is provided on the main surface of semiconductor substrate 1S and is formed of
conductor film 3 patterned, so lower electrode interconnection M0 (lower The electrodes M0E)
can be separated in the X direction in FIGS. 1 to 4 to form a plurality of channels, and the
transducers 20 can be controlled in a matrix to realize a higher performance ultrasonic
transducer. it can.
[0203]
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60
When lower electrode wiring M0 (lower electrode M0E) is formed of patterned conductive film 3
as in the first to eighth embodiments, the upper surface end 121 shown in FIG. ) Is formed on the
lower electrode wiring M0 (lower electrode M0E), and this corner (upper surface end 121) is
sharper than the stepped portion 123a of the upper electrode wiring M1 due to the hollow
portion VR, so that the electric field is concentrated easy. For this reason, the upper electrode
M1E (upper electrode) is formed in the case where the lower electrode M0E is formed by the
patterned conductor film 3 than when the lower electrode M0E is formed by a part of the
semiconductor substrate (n-type semiconductor region 41). Since a drop in dielectric breakdown
voltage between the wiring M1) and the lower electrode M0E (n-type semiconductor region 41)
is more pronounced, the film structures of the insulating films 5 and 7 are devised as in the first
to eighth embodiments and the upper and lower It is extremely important to improve the
withstand voltage between the electrodes of the
[0204]
Further, Embodiment 9 can be combined with Embodiments 2 to 8 above, and in the structure of
Embodiment 9, the film structure of insulating films 5 and 7 can be changed as in Embodiments
2 to 8 above.
[0205]
Although the lower electrode M0E is formed of the n-type semiconductor region 41 in the ninth
embodiment, ion implantation of, for example, B (boron) or BF2 is performed as the lower
electrode M0E instead of the n-type semiconductor region 41. Thus, a p-type semiconductor
region may be formed.
[0206]
The materials constituting the CMUT cell shown as the above-mentioned first to ninth
embodiments show one of the combinations.
A metal film with low resistance is used for the upper and lower electrodes (upper electrode M1E
and lower electrode M0E), and the formation of the interelectrode insulating film (insulating
films 5 and 7) and the sacrificial film (film for sacrificial film pattern 6) The case of performing
the deposition by the plasma CVD method capable of deposition at a low temperature of about
400 ° C. so as not to melt the film has been described.
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61
However, the upper and lower electrodes (upper electrode M1E and lower electrode M0E) may
be conductive films, and for example, polycrystalline silicon films (doped polysilicon films) that
can withstand high temperature processes of 1000 ° C. or higher may be used. it can. In this
case, the deposition of the silicon oxide film and the silicon nitride film constituting the interelectrode insulating film (insulating films 5 and 7) is a low pressure chemical vapor deposition
(LPCVD) process which is a process at a higher temperature than the plasma CVD method. )
Method may be used.
[0207]
In addition, after deposition of the silicon oxide film or silicon nitride film for the insulating films
5 and 7, heat treatment is added in any of the subsequent manufacturing steps to reduce the
traps in these insulating films and improve the film quality. May be
[0208]
In addition, the material of the sacrificial film (film for the sacrificial film pattern 6) is also a
material surrounding the sacrificial film pattern 6, such as amorphous silicon or polycrystalline
silicon (sacrificial film pattern 6 of the insulating films 5 and 7) It is sufficient if it is a material
that can ensure etching selectivity with the part in contact with.
[0209]
In addition, although the CMUT cell has a hexagonal shape in FIGS. 3 to 5 above, the shape is not
limited to this, and for example, it may be circular or rectangular.
[0210]
As mentioned above, although the invention made by the present inventor was concretely
explained based on the embodiment, the present invention is not limited to the embodiment, and
can be variously changed in the range which does not deviate from the summary. Needless to
say.
[0211]
The present invention is preferably applied to, for example, a semiconductor device having an
ultrasonic transducer.
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[0212]
FIG. 1 is an overall plan view of a semiconductor chip constituting a semiconductor device
according to an embodiment of the present invention.
It is a principal part enlarged plan view of the semiconductor chip of FIG.
It is a principal part enlarged plan view of the semiconductor chip of FIG.
It is a principal part enlarged plan view of the semiconductor chip of FIG.
It is principal part sectional drawing of the semiconductor chip of FIG.
It is principal part sectional drawing of the semiconductor chip of FIG. FIG. 7 is a cross-sectional
view of essential parts in the process of manufacturing a semiconductor device in Embodiment 1
of the present invention. FIG. 8 is a cross-sectional view of main parts of the semiconductor
device in the manufacturing process continued from FIG. 7; FIG. 9 is a cross-sectional view of
main parts of the semiconductor device in the manufacturing process continued from FIG. 8; FIG.
10 is a cross-sectional view of main parts of the semiconductor device in the manufacturing
process continued from FIG. 9; FIG. 11 is a cross-sectional view of main parts of the
semiconductor device in the manufacturing process continued from FIG. 10; FIG. 12 is a crosssectional view of the essential part in the manufacturing process of the semiconductor device
subsequent to FIG. 11; FIG. 13 is a cross-sectional view of the essential part in the manufacturing
process of the semiconductor device subsequent to FIG. 12; FIG. 14 is another cross-sectional
view of the essential part in the same manufacturing process as FIG. 13; FIG. 15 is a crosssectional view of main parts of the semiconductor device in the manufacturing process continued
from FIG. 14; FIG. 16 is a cross-sectional view of main parts of the semiconductor device in the
manufacturing process continued from FIG. 15; FIG. 17 is a cross-sectional view of main parts of
the semiconductor device in the manufacturing process continued from FIG. 16; FIG. 17 is a
cross-sectional view of main parts of the semiconductor device in the manufacturing process
continued from FIG. 16; It is principal part sectional drawing of the semiconductor device of a 1st
comparative example. It is principal part sectional drawing of the semiconductor device of a 2nd
comparative example. It is a graph which shows the result of having evaluated the proof pressure
of the insulating film between electrodes. It is a graph which shows the result of having applied
the voltage between electrodes for a long time, and having measured the shift amount of the
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capacity ¦ capacitance-voltage curve. It is a graph which shows typically the capacity ¦
capacitance-voltage curve (CV curve) before and behind which applied the voltage between
electrodes for a long time. It is explanatory drawing of the probe of the ultrasonic echo
diagnostic apparatus to which the semiconductor device which is one embodiment of this
invention is applied. It is principal part sectional drawing of the semiconductor device of
Embodiment 2 of this invention. It is principal part sectional drawing of the semiconductor
device of Embodiment 2 of this invention. FIG. 26 is a plan view of the essential part in the
manufacturing process of the semiconductor device in Embodiment 2 of the present invention; It
is principal part sectional drawing of the semiconductor device of Embodiment 3 of this
invention. It is principal part sectional drawing of the semiconductor device of Embodiment 3 of
this invention. It is a principal part top view in the manufacturing process of the semiconductor
device of Embodiment 3 of the present invention. It is principal part sectional drawing of the
semiconductor device of Embodiment 4 of this invention. It is principal part sectional drawing of
the semiconductor device of Embodiment 4 of this invention. It is a principal part top view in the
manufacturing process of the semiconductor device of Embodiment 4 of this invention. It is a
principal part top view in the manufacturing process of the semiconductor device of Embodiment
4 of this invention. It is principal part sectional drawing of the semiconductor device of
Embodiment 5 of this invention. It is principal part sectional drawing of the semiconductor
device of Embodiment 5 of this invention. It is a principal part top view in the manufacturing
process of the semiconductor device of Embodiment 5 of this invention. It is a principal part top
view in the manufacturing process of the semiconductor device of Embodiment 5 of this
invention.
It is principal part sectional drawing of the semiconductor device of Embodiment 6 of this
invention. It is principal part sectional drawing of the semiconductor device of Embodiment 6 of
this invention. It is a principal part top view in the manufacturing process of the semiconductor
device of Embodiment 6 of this invention. It is a principal part top view in the manufacturing
process of the semiconductor device of Embodiment 6 of this invention. It is principal part
sectional drawing of the semiconductor device of Embodiment 7 of this invention. It is principal
part sectional drawing of the semiconductor device of Embodiment 7 of this invention. It is a
principal part top view in the manufacturing process of the semiconductor device of Embodiment
7 of this invention. It is a principal part top view in the manufacturing process of the
semiconductor device of Embodiment 7 of this invention. It is principal part sectional drawing of
the semiconductor device of Embodiment 8 of this invention. It is principal part sectional
drawing of the semiconductor device of Embodiment 8 of this invention. FIG. 26 is a plan view of
the main part in the manufacturing process of the semiconductor device in the eighth
embodiment of the present invention; FIG. 26 is a plan view of the main part in the
manufacturing process of the semiconductor device in the eighth embodiment of the present
invention; It is principal part sectional drawing of the semiconductor device of Embodiment 9 of
this invention. It is principal part sectional drawing of the semiconductor device of Embodiment
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9 of this invention. FIG. 35 is a plan view of the main part in the manufacturing process of the
semiconductor device in the ninth embodiment of the present invention; FIG. 35 is a plan view of
the main part in the manufacturing process of the semiconductor device in the ninth
embodiment of the present invention;
Explanation of sign
[0213]
DESCRIPTION OF SYMBOLS 1 semiconductor chip 1S semiconductor substrate 1Sa 1st main
surface 1Sb 2nd main surface 2 insulating film 3 conductor film 4,4a insulating film 5 insulating
film 5a, 5c, 5d, 5f silicon oxide film 5b, 5e silicon nitride film 6 sacrificial film pattern Reference
Signs List 7 insulating film 7a, 7c, 7d, 7f silicon oxide film 7b, 7e silicon nitride film 8 conductor
film 9 insulating film 10 hole 11 insulating film 13 insulating film 20 vibrator 30 probe 30a
probe case 30b acoustic lens 41 n-type semiconductor region 105a , 107a Silicon oxide film
105b, 107b Silicon nitride film 121 Upper surface end 122, 124 Path 123, 123a Stepped portion
125a, 127 Silicon oxide film 125b, 127b Silicon nitride film BP1, BP2 Pad CA CMUT region M0
Lower electrode wiring M0E Lower electrode M1 upper electrode wiring 1C connecting portion
M1E upper electrode VR cavity
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