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Verilog Intro: Part 2
Procedural Blocks
• There are two types of procedural blocks in Verilog.
– initial for single-pass behavior: initial blocks execute only
once at time zero (start execution at time zero).
– always for cyclic behavior: always blocks loop to execute
over and over again, in other words as the name implies, it
always executes.
• Procedural assignment may only appear in initial and always
constructs.
• The initial and always constructs are used to model
sequential logic.
• Continuous statement is used to model combinational logic.
Example: Initial Block
module initial_example;
reg clk,reset,enable,data;
initial
begin
clk = 0;
reset = 0;
The initial block is executed at time 0.
Initial block just execute all the statements
enable = 0;
within begin and end statements.
data = 0;
end
endmodule
Control Constructs
•
•
Control Constructs
– Can be used in the procedural sections of code.
Selection
– if statement:
if (A == 4)
B = 2;
else
begin
B = 4;
end
– case statements:
case (<expression>)
<value1>: <statement>
<value2>: <statement>
default: <statement>
endcase
Example: 4-1 MUX in behavioral (1)
module mux4 (Y,sel, A, B, C, D);
input [1:0] sel; // 2-bit control signal
A
input A, B, C, D;
B
output Y;
C
reg Y; // target of assignment
D
always @(sel or A or B or C or D)
if(sel == 2’b00) Y = A;
else if(sel == 2’b01) Y = B;
sel[1:0]
else if(sel == 2’b10) Y = C;
else if(sel == 2’b11) Y = D;
endmodule
Y
Example: 4-1 MUX in behavioral (2)
// 4-1 mux using case statement
module mux4 (Y,sel, A, B, C, D);
input [1:0] sel; // 2-bit control signal
input A, B, C, D;
output Y;
reg Y; // target of assignment
always @(sel or A or B or C or D)
case (sel)
2’b00: Y = A;
2’b01: Y = B;
2’b10: Y = C;
2’b11: Y = D;
endcase
endmodule
A
B
C
D
Sel[1:0]
Y
Example: 4-1 MUX in behavioral (3)
// 4-1 mux using case statement
module mux4 (q, select, d);
input [1:0] select; // 2-bit control signal
input [3:0] d;
output q;
reg q; // target of assignment
always @(select or d)
case (select)
2’b00: q = d[0];
2’b01: q = d[1];
2’b10: q = d[2];
2’b11: q = d[3];
endcase
endmodule
Example: 4-1 MUX in structural
module mux4(q, select, d);
input[1:0] select;
input[3:0] d;
output q;
wire q1, q2, q3, q4, NOTselect0, NOTselect1;
not n1( NOTselect0, select[0] );
not n2( NOTselect1, select[1] );
and a1( q1, NOTselect0, NOTselect1, d[0] );
and a2( q2, select[0], NOTselect1, d[1] );
and a3( q3, NOTselect0, select[1], d[2] );
and a4( q4, select[0], select[1], d[3] );
or o1( q, q1, q2, q3, q4 );
endmodule
4-bit Full Adder using 1-bit Full Adder
module FourBitAdder( sum, c_out, x, y, c_in);
output [3:0] sum;
output c_out;
input [3:0] x, y;
input c_in;
wire c1, c2, c3;
fulladder fa0( sum[0], c1, x[0], y[0], c_in );
fulladder fa1( sum[1], c2, x[1], y[1], c1 );
fulladder fa2( sum[2], c3, x[2], y[2], c2 );
fulladder fa3( sum[3], c_out, x[3], y[3], c3 );
endmodule
module fulladder( sum, c_out, x, y, c_in );
output sum, c_out;
input x, y, c_in;
wire a, b, c;
xor( a, x, y);
xor( sum, a, c_in );
and( b, x, y );
and( c, a, c_in );
or( c_out, c, b );
endmodule
Repetition
•
// for loop
for(i = 0; i < 10; i = i + 1) begin
$display(“i = %d", i); end
•
•
//while loop
i = 0;
while(i < 10)
begin
$display(“i = %d", i);
i = i + 1;
end
// repeat loop
repeat (5) //repeats the block 5 times,
begin
$display(“i = %d", i);
i = i + 1;
end
Blocking and Non-blocking Procedural
Assignments
• The blocking assignment statement (= operator)
acts much like in traditional programming
languages. Blocking statement must complete
execute before the next statement in the
behavior can execute.
• The non-blocking (<= operator) evaluates all the
right-hand sides for the current time unit and
assigns the left-hand sides at the end of the time
unit. Non-blocking assignment statements
execute concurrently rather than sequentially.
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