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```The Micro Architecture Level
Mic-1 architecture on Tanenbaum’s book
Dept. of Computer Science
Virginia Commonwealth University
Mic-1 block diagram
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1. Why the C bus is represented as a bit map?
while B bus register is encoded in a 4 bit field
Only one register can
yet more than one
register can be
from C bus
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2. Give a circuit diagram for “High bit”.
F =(JAMZ AND Z) OR (JAMN AND N) OR NEXT_ADDRESS[8]
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JAMZ
JAMN
Z
MPC8
N
JAMC



MPC7
MBR7












MPC0
MBR0
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MPC points to the next
microinstruction.
it is computed from
JAM fields
the ALU
status N and Z,
the MBR
(JAMZ and Z) or
(JAMN and Z)
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3. Next address = 0x1FF and use JMPC?
Does it make sense? What if Next address is 0xFF?
bbbbbbbb (MBR)
No, Meaningless
Next address is usually, 0x00 or 0x100
Why?
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4. What if add k=5 after IF?
K=5
BIPUSH 5
ISTORE k
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5 IJVM translation of i= k + n + 5
BIOUSH 5
BIOUSH 5
ISTORE i
ISTORE i
5
n
k
k
k
n
k
k+n
5
k+n
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n+5
k
k+n+5
k+n+5
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6. Give the JAVA statement
ISUB
BIPUSH 7
i = j-n-7 + j-n-7
ISUB
DUP
ISTORE i
j
n
j
j-n
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j-n
j-n-7
11
j-n-7
j-n-7
2(j-n-7)
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7. Is it possible?
If (Z) go to L1; else go to L2 // on page 259
0x75
0x40
0x140
Z : upper half or lower half
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8.Why not: if_cmpeq3 Z = TOS-MDR;rd
If_icmpeq1
MAR=Sp=Sp-1; rd
If_icmpeq2
MAR=SP=SP-1
If_icmpeq3
H=MDR; rd
If_icmpeq4
OPC = TOS
If_icmpeq5
TOS = MDR
If_icmpeq6
Z=OPC-H; if (Z) go to T; else go to F
The only possible subtrahend is H
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9. How long it will takes?
i = j+ k; w/ 2.tGHz Mic1
Main
PC = PC +1; fetch; go to (MBR)
Main
PC = PC +1; fetch; go to (MBR)
Main
PC = H=LV
PC +1; fetch; go to (MBR)
ISTORE1
= SP-1; rd;
ISTORE2
MAR=MBRU+H
ISTORE3 H=TOS
MDR=TOS; wr
Iload4 PC = PC +; fetch; wr
= TOS+MDR-H;wr;
ISTORE4
wr goto main
Iload5 TOS = MDR; go to main
ISTORE5
PC = PC +1; fetch
ISTORE6
ISTORE
TOS = MDRT; goto main
ISTORE(7)
23microinstructions *0.4nsec = 9.2 nsec
2.5GHz means 1 cycle / (1 / 2.5* G)sec = 0.4nanosec
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Microinstruction
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Microinstruction
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0x15 0x03
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0x60
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Microinstruction: istore
ISTORE I
0x36 0x01
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Microinstruction: Homework
by Nov 28
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10 speed with Mic-2
Mic1 : 2 bus architecture
Mic2 : simplified decoding, 3 bus, IFU
Mic3 : 4 stage pipeline
Mic4 : 7 state pipeline
What is
IFU
common?
(Instruction Fetch Unit)
PC is passed
Independently
through theincrement
CPU and incremented
PC and fetch next byte
PC is used
(assemble
to fetch 8next
andbyte
16 bit operands)
Depends
Operands
on the
are opcode
make
memory
available the next 8 or 16 bit
whether or not doing so makes sense.
Operand are written to memory
ALU does computation and results are stored back
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Mic-2
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How to design IFU?
Fetch 4 bytes and load into shifter
Feed into MBR1 and MBR2
Whenever PC is changed, IFU must be changed
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ISTORE(7)
23microinstructions *0.4nsec = 9.2 nsec
Main
PC = PC +1; fetch; go to (MBR)
H=LV
MAR=MBRU+H; rd
MAR=SP=SP+1
PC = PC +; fetch; wr
TOS = MDR; go to main
2.5GHz means 1 cycle / (1 / 2.5* G)sec = 0.4nanosec
MAR = LV + MBR1U;rd
MAR=SP=SP+1
TOS=MDR;wr;goto(MBR1)
as in Fig. 4-30 pp282-283
ISTORE(5)
14 instn*0.4 = 5.6 nanosec
23microinstructions *0.4nsec = 9.2 nsec
5.6/9.2 = x/100
2.5GHz means 1 cycle / (1 / 2.5* G)sec = 0.4nanosec
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x = 60.87sec
Hongsik Choi
11 Write microcode for POPTWO
Pop1
MAR = SP -1; rd
Pop2
Pop3
TOS = MDR; goto Main
PopTwo1
SP=SP−1
PopTwo2
MAR=SP=SP−1; rd
PopTwo3
PopTwo4
TOS=MDR; gotoMain1
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How should modify IJVM to make the best
use of it.
Local 0 is the link pointer, (rarely used)
Let LV point first local variables as an offset( -1)
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13 ISHR (Arithmetic Shit Right)
Use top two values, replacing with one value, Second word is operand to be
shifted. It should be shifted between o-31 depending on the value of first
Opcode for ISHR is 122 (0x7A)
a. What is the arithmetic operation equivalent to shit right with a
count of 2?
Extra: due Nov. 29th ?
b. Write microcode.
00000…1101
000000…110
0000000…11
00000000…1
13
3
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Floor(fisrst)/2second
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14 ISHL
Fisrst*2second
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15 INVOKRVIRTUAL
It needs to know how many parameters. Why?
Compute the base address of the new local variable frame
by subtracting off the number of parameters from the stack
pointer and setting LV to point to OBJREF
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dlaod6
MAR = LV + MBR1U; rd
H = MAR + 1
MAR = SP = SP +1; wr
MAR = H; rd
MAR = SP = SP + 1; wr
TOS = MDR; goto (MBR)
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17 finite state machine
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18 equivalents?
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19 finite state machine
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20 IFU with a 5 byte shifter register
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21 larger shifter for IFU
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22 Mic 2 : go to
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23 speed with Mic-2
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24 Mic-4
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25 two level cache
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26 3 way cache?
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27 pipeline
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28 prefetch
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29 cycle 6
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30 dependency in pipeline
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31 Rewrite Mic-1 intepreter
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32 write simulator
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```
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