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Computer Memory
Basic Concepts
Lecture for CPSC 5155
Edward Bosworth, Ph.D.
Computer Science Department
Columbus State University
The Memory Component
• The memory stores the instructions and data
for an executing program.
• At this level, we are considering memory as a
unit without structure. Cache memory will be
covered fully in a future lecture.
Memory Addressability
• Memory is characterized by the smallest
addressable unit:
Byte addressable
the smallest unit is an 8–bit byte.
Word addressable
the smallest unit is a word, usually 16 or 32 bits.
• Almost all modern computers use byte
addressability to simplifies processing of
character data.
Memory Control
• The CPU has 2 registers dedicated to handling
memory.
• The MAR
(Memory Address Register)
holds the address being accessed.
• The MBR
(Memory Buffer Register)
holds the data being written to the memory
or being read from the memory. This is
sometimes called the Memory Data Register.
Memory Control Signals
• Read / Write Memory must do three actions:
1. READ copy contents of an addressed word
into the MBR
2. WRITE copy contents of the MBR into the
location being addresses.
3. NOTHING
the memory is expected to
retain the contents written into it until
those contents have been rewritten.
One Option for Memory Control
• The CPU can issue one of two control signals.
These are usually asserted high.
•
READ WRIT Action
E
0
0
Nothing. The memory is not active.
0
1
The CPU writes to memory
1
0
The CPU reads from memory
1
1
This is a problem, which must be solved
by a design decision.
Asserting Control Signals
• A control signal is a binary signal with only
two values: 0 (logic low) and 1 (logic high).
• When a control signal is to activate some
circuit element, it is said to be asserted.
• An active high signal is asserted when its
value is 1. It is denoted by the signal name.
• An active low signal is asserted when its value
is 0. It is denoted by appending a “#” to its
name, as in Select#.
Alternate Notation for Active Low
• A signal asserted low might be denoted as
• The first notation is older, and harder to depict
using word processors.
• A two-value control signal enables one of two
actions depending on its value. A signal to
indicate either read or write might be denoted
Modern Memory Control
• Most modern designs avoid the READ and WRITE
control signals, using Select# and R/W#
• If R/W# = 0, a memory write is called for.
If R/W# = 1, a memory read is called for.
Select#
1
R/W#
0
Action
Memory contents are not changed.
1
1
Memory contents are not changed.
0
0
CPU writes data to the memory.
0
1
CPU reads data from the memory.
(Classical) Memory Timings
Memory Access Time is defined in terms of reading
from memory. It is the time between the address
becoming stable in the MAR and the data becoming
available in the MBR.
Memory cycle time is the minimum time interval
between two independent memory accesses.
Synchronous Memory Timings
• Synchronous memory, typically SDRAM, is
rated by the speed of the memory bus.
• The speed is normally quoted in megahertz, as
in 166 MHz or 250 MHz, or some other value.
• A 250 MHz memory can be attached to a 250
MHz synchronous memory bus, and transfer
data at the rate of 250 million transfers/sec.
• This is one transfer every 4 nanoseconds.
• The data transfer rate depends on the width
of the data bus, often as high as 64 bits.
RAM and ROM
• Technically, the term “RAM” stands for
“random access memory” with no further
connotations.
• In common usage, the term RAM refers to
memory that is “read/write”; the CPU can
both read from and write to RAM.
• The term “ROM” stands for “read only
memory”. In standard operations, the CPU
cannot change the values stored in ROM.
Varieties of ROM
1. “Plain ROM” The contents of the memory
are set at manufacture and cannot be
changed without destroying the chip.
2. PROM The contents of the chip are set by a
special device called a “PROM Programmer”.
Once programmed the contents are fixed.
3. EPROM is same as a PROM, but that the
contents can be erased and reprogrammed
by the PROM Programmer device.
Memory Mapped Input / Output
• The old PDP–11/20 supported a 16–bit address space. This
supported addresses in the range 0 through 65,535 or 0 through
0177777 in octal.
• Addresses 0 though 61,439 were reserved for physical memory.
In octal these addresses are given by 0 through 167,777.
• Addresses 61,440 through 65,535 (octal 170,000 through 177,777)
were
reserved for registers associated with Input / Output devices.
• Examples: CR11 Card Reader
177,160
Control & Status Register
177,162
Data buffer 1
177,164
Data buffer 2
• Reading from address 0177162 would access the card reader data
buffer.
Memory Mapped I/O in the MIPS
The Linear View of Memory
• This logical view is not easily implemented.
Standard Memory Organization
• Modern computer memory is organized as a
collection of modules connected to a bus.
• Each module comprises 8 or 9 data chips.
Module Organization
• A standard module will have 8 data chips, one
for each bit in the Memory Buffer.
• Assigning one bit per chip is more efficient.
Memory Chip Organization
• As an example, here is a 4 megabit chip. It is
organized as a 2-D array.
Two Options for Addressing
• The option at left has 28 pins, the option at
right has 19 pins. The signals RAS# and CAS#
indicate the meaning of the 11-bit address.
Memory Interleaving
• Suppose a 64MB memory made up of the
4Mb chips discussed above.
• We organize the memory into 4MB banks.
• The memory thus has 16 banks, each of 4MB.
• 16 = 24
4 bits to select the bank
4M = 222
22 bits address to each chip
• Not surprisingly, 64M = 226.
Two Interleaving Options
• The type of interleaving dictates how the
memory address is divided.
• Low-order interleaving
Bits
Use
25 – 4
Address to the chip
3–0
Bank Select
• High-order interleaving (banking)
Bits
25 – 22
21 – 0
Use
Bank Select
Address to the chip
Speed Up Access by Interleaving Memory
• Suppose an 8–way low–order interleaved
memory. The chip timings are:
80 nanosecond cycle time, and
40 nanosecond access time.
• Each chip has the following timing diagram.
Timings for the Interleaved Memory
Faster Memory Chips
• After the row address is asserted, a number of
column reads may proceed.
SDRAM
• SDRAM is synchronous dynamic RAM.
• In SDRAM, the memory transfers take place on a
timing dictated by the memory bus clock rate. In
“plain” SDRAM, the transfers all take place on the
rising edge of the bus clock.
• In DDR SDRAM (Double Data Rate), the transfers
take place on both the rising and falling clock edges.
A Synchronous Bus Timing Diagram
SDRAM with a Wide Bus
• DDR–SDRAM makes two transfers for every cycle of the
memory bus, 1 on the rising edge of the clock cycle
1 on the falling edge of the clock cycle.
• For a 100 MHz memory bus, DDR–SDRAM would have
200 million transfers per second.
• Now consider a 64–bit data bus, which can transfer
64 bits (8 bytes) at a time.
• Thus our sample DDR–SDRAM bus would transfer
1,600 million bytes per second.
• This is 1.49 GB / second, as 1 GB = 232 bytes.
Word Addressing in a
Byte Addressable Machine
• Each 8–bit byte has a distinct address.
• A 16-bit word at address Z contains bytes at
addresses Z and Z + 1.
• A 32-bit word at address Z contains bytes at
addresses Z, Z + 1, Z + 2, and Z + 3.
• Question: How is the value stored in a 32-bit
register stored in computer memory?
Big–Endian vs. Little–Endian
• Address Big-Endian Little-Endian
•
Z
01
04
•
Z+1
02
03
•
Z+2
03
02
•
Z+3
04
01
Big–Endian vs. Little–Endian
Example: “Core Dump” at Address 0x200
• Here is a sample memory map.
Address
Contents
0x200
02
0x201
04
0x202
06
0x203
08
• What is the 32-bit integer stored at address 0x200?
• Big Endian: The number is 0x02040608.
Its decimal value is
22563 + 42562 + 62561 + 81 = 33,818,120
• Little Endian: The number is 0x08060402.
Its decimal value is
82563 + 62562 + 42561 + 21 = 134,611,970.
Another “Core Dump”
• Here is the same memory map.
Address 0x200 0x201 0x202 0x203
Contents
02
04
06
08
• The 16–bit integer stored at address 0x200 is stored in
the two bytes at addresses 0x200 and 0x201.
• Big Endian:
The value is 0x0204.
The decimal value is 2256 + 4 = 516
• Little Endian:
The value is 0x0402.
The decimal value s 4256 + 2 = 1,026
Evolution of Modern Memory
Year
Cost per MB
in US $
Actual component
Size (KB) Cost
Speed
nsec.
Type
1957
1959
1965
1970
411,041,792.00
67,947,725.00
2,642,412.00
734,003.00
0.0098
0.0098
0.0098
0.0098
392.00
64.80
2.52
0.70
10,000
10,000
2,000
770
transistors
vacuum tubes
core
core
1975
1981
1985
1990
1996
2001
2006
2008
2010
49,920.00
4,479.00
300.00
46.00
5.25
15¢
7.3¢
1.0¢
1.22¢
4
64
2,048
1,024
8,192
128 MB
2,048 MB
4,096 MB
8,192 MB
159.00
279.95
599.00
45.50
42.00
18.89
148.99
39.99
99.99
??
??
??
80
70
133 MHz
667 MHz
800 MHz
1333 MHz
static RAM
dynamic RAM
DRAM
SIMM
72 pin SIMM
DIMM
DIMM DDR2
DIMM DDR2
DIMM DDR2
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