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Low Power Design
in CMOS
Digital Integrated Circuits
Low Power Design
© Prentice Hall 1995
Why worry about power?
-- Heat Dissipation
microprocessor power dissipation
source : arpa-esto
DEC 21164
Digital Integrated Circuits
Low Power Design
© Prentice Hall 1995
Evolution in Power Dissipation
Digital Integrated Circuits
Low Power Design
© Prentice Hall 1995
BATTERY
(40+ lbs)
N om inal C apacity (W att-hours / lb)
Why worry about power —
Portability
50
Rechargable Lithium
40
Ni-Metal Hydride
30
20
Nickel-Cadium
10
0
65
70
75
80
85
90
95
Year
Multimedia Terminals
Expected Battery Lifetime increase
Laptop Computers
over next 5 years: 30-40%
Digital Cellular Telephony
Digital Integrated Circuits
Low Power Design
© Prentice Hall 1995
Where Does Power Go in CMOS?
• D y na m ic P ow er C o n su m p tio n
C h a rg in g a n d D is c h a rg in g C a p a c ito rs
• S h or t C irc uit C u rre nts
S h o rt C irc u it P a th b e tw e e n S u p p ly R a ils d u rin g S w itc h in g
• Le aka ge
L e a k in g d io d e s a n d tra n s is to rs
Digital Integrated Circuits
Low Power Design
© Prentice Hall 1995
Dynamic Power Consumption
Vdd
V in
V out
CL
E n e r g y /tr a n s itio n = C L * V d d 2
P o w e r = E n e r g y /tr a n s itio n * f = C L * V dd 2 * f
N o t a fu n c tio n o f tr a n si sto r siz e s!
N e e d t o r e d u c e C L , V dd , a n d f to re d u ce p o w e r.
Digital Integrated Circuits
Low Power Design
© Prentice Hall 1995
Dynamic Power Consumption - Revisited
Pow e r = E ne r gy/tr ans ition * t ran sit ion r at e
= C L * V d d 2 * f0  1
= C L * Vdd2 * P0 1* f
= C E F F * V d d2 * f
Po w er D iss ip a tio n is D a ta D e pe nd en t
Fu nc tio n o f Sw itc hing A c tiv ity
C E F F = E ff ec ti ve C apac itanc e = C L * P 0 1
Digital Integrated Circuits
Low Power Design
© Prentice Hall 1995
Power Consumption is Data Dependent
E xam ple: S tatic 2 In put N O R G ate
A ss um e :
P(A =1) = 1/2
P(B = 1) = 1/2
T he n:
P(O ut= 1) = 1/4
P(0  1)
= P (O ut= 0).P(O ut= 1)
= 3/4  1/4 = 3/16
C E F F = 3/16 * C L
Digital Integrated Circuits
Low Power Design
© Prentice Hall 1995
Transition Probabilities for Basic Gates
Digital Integrated Circuits
Low Power Design
© Prentice Hall 1995
Transition Probability of 2-input NOR Gate
Digital Integrated Circuits
Low Power Design
© Prentice Hall 1995
Problem: Reconvergent Fanout
A
X
B
Z
R econvergence
P(Z = 1) = P(B = 1) . P (X = 1 | B = 1)
B e com e s c om plex an d intr actab le r eal fast
Digital Integrated Circuits
Low Power Design
© Prentice Hall 1995
How about Dynamic Circuits?
VDD

Mp
Out
I n1
I n2
I n3
PDN

Me
Pow er is O nly D issipate d w he n O ut= 0!
C E F F = P (O u t=0).C L
Digital Integrated Circuits
Low Power Design
© Prentice Hall 1995
4-input NAND Gate
E xam ple: D ynam ic 2 I npu t N O R G ate
A ss um e :
P(A =1) = 1/2
P(B = 1) = 1/2
T he n:
P(O ut= 0) = 3/4
C E F F = 3/4 * C L
S w itc h in g A c tiv ity Is A lw ay s H ig h e r in D y n a m ic C ircu its
Digital Integrated Circuits
Low Power Design
© Prentice Hall 1995
Transition Probabilities for Dynamic Gates
Sw itching Act ivity for P re charg ed D ynam ic G ates
P 0 1 = P 0
Digital Integrated Circuits
Low Power Design
© Prentice Hall 1995
Glitching in Static CMOS
a ls o ca lled : dy na m ic ha zard s
X
A
B
Z
C
ABC
10 1
0 00
X
Z
U nit D e la y
O b serve: N o glitch in g in d yn am ic circu its
Digital Integrated Circuits
Low Power Design
© Prentice Hall 1995
Example 1: Chain of NOR Gates
out1
out2
out3
out4
out5
1
...
6.0
out8
V (V olt)
4.0
out2
2.0
out4
out6
out1
out3
out5
out7
0.0
0
Digital Integrated Circuits
1
t (nsec)
2
Low Power Design
3
© Prentice Hall 1995
Example 2: Adder Circuit
Add0
Cin
Add1
S um O utput V oltage, V olts
S0
Add2
Add14
S2
S14
S1
4.0
Add15
S15
4
S15
6
2.0
3
S10
Cin
5
S1
2
0.0
0
5
10
Time, ns
Digital Integrated Circuits
Low Power Design
© Prentice Hall 1995
How to Cope with Glitching?
0
F1
0
1
F1
F2
0
0
2
F3
F3
0
1
0
0
0
F2
1
Eq ualize L engths of T im in g P aths T hrough D esign
Digital Integrated Circuits
Low Power Design
© Prentice Hall 1995
Short Circuit Currents
V dd
V in
V ou t
CL
I V D D (m A)
0 .15
0 .10
0 .05
0. 0
Digital Integrated Circuits
1.0
2.0
3.0
V in ( V)
4.0
5.0
Low Power Design
© Prentice Hall 1995
Impact of rise/fall times on short-circuit
currents
VD D
VDD
I SC 
V in
I SC   I M AX
V out
CL
CL
L arge capacitive load
Digital Integrated Circuits
V ou t
V in
S m all capacitive load
Low Power Design
© Prentice Hall 1995
Short-circuit energy as a function of slope
ratio
E / E
8
VD D = 5 V
W /L | P = 7.2  m /1.2  m
W /L |N = 2.4  m /1.2  m
7
6
5
4
3
2
V D D = 3.3 V
1
0
r
0
1
2
3
4
5
T h e p ow er d issip ation d u e to sh ort circu it cu rren ts is
m in im ized b y m atch in g th e
rise/fall tim es of th e in p u t an d ou tp u t sign als.
Digital Integrated Circuits
Low Power Design
© Prentice Hall 1995
Static Power Consumption
V dd
I sta t
V out
V i n =5V
CL
P s ta t = P ( In = 1 ) .V d d . I s t a t
• D o m ina tes o ver d yn am ic c on su m p tion
• N ot a fu nc tio n o f sw itc hin g fre qu en cy
Digital Integrated Circuits
Low Power Design
© Prentice Hall 1995
Leakage
V dd
V ou t
D ra in J u n ctio n
L e ak a g e
S u b -T h re sh o ld
C ur ren t
S ub -T hr esh o ld C u rre nt D o m in an t F ac tor
Digital Integrated Circuits
Low Power Design
© Prentice Hall 1995
Sub-Threshold in MOS
 ID
V T =0.2
V T =0.6
VGS
Lo w er B o u nd on Th re sh old to P rev en t L ea kag e
Digital Integrated Circuits
Low Power Design
© Prentice Hall 1995
Power Analysis in SPICE
VDD
iDD
+
-
P av
C
C irc u it
k iD D
R
U n d e r T es t
E q u iv a le n t C irc u it fo r M e a s u rin g P o w e r in S P IC E
Digital Integrated Circuits
Low Power Design
© Prentice Hall 1995
Design for Worst Case
V DD
VDD
1
A
1
F
2
CL
D
B
4
C
4
2
A
B
B
2
F
A
2
A
D
2
1
B
2 C
2
H ere it is assum ed that R p = R n
Digital Integrated Circuits
Low Power Design
© Prentice Hall 1995
N O R M A LI ZED PO W E R -D E LA Y PR O D U C T
Reducing Vdd
1.5
P x td = E t = C L * Vdd 2
1.00
0.70
0.50
0.30
0.20
quadratic dependence
0.15
E(Vdd=2)
E(Vdd=5)
0.1
=
(CL) * (2)2
(CL) * (5)2
51 stage ring oscillator
0.07
E(Vdd=2)  0.16 E(Vdd =5)
0.05
8-bit adder
0.03
1
2
5
Vdd (volts)
Strong function of voltage (V 2 dependence).
Relatively independent of logic function and style.
Power Delay Product Improves with lowering VDD.
Digital Integrated Circuits
Low Power Design
© Prentice Hall 1995
Lower Vdd Increases Delay
7. 50
7. 00
m ult ip lie r
2.0 m tec hn ology
c lo c k g en er a tor
Td =
6. 50
C L * V dd
I
N O R M A L IZ ED D E L A Y
6. 00
5. 50
5. 00
I ~ (V d d - V t ) 2
4. 50
4. 00
3. 50
ring osc illat or
3. 00
2. 50
m ic r oc od ed D SP ch ip
T d (V d d = 5)
2. 00
1. 50
(2) * (5 - 0.7) 2
T d (V d d = 2)
=
(5) * (2 - 0.7) 2
add er

adde r ( SP IC E )
1. 00
2. 00
4. 00
4
6.0 0
V dd ( vo lt s)
R elatively in d ep en d en t of logic fu n ction an d style.
Digital Integrated Circuits
Low Power Design
© Prentice Hall 1995
Lowering the Threshold
D ela y
I
2V t
Vdd
D
Vt = 0
V t = 0.2
VGS
R ed u ces th e S p eed Lo ss , B u t In cr eas es L eak ag e
In ter est ing D esig n A p pr oach :
D E SIG N FO R P L e ak a g e = = P D y na m ic
Digital Integrated Circuits
Low Power Design
© Prentice Hall 1995
Transistor Sizing for Power Minimization
L ow er C ap acitan ce
H igh er V oltage
S m all W /L ’s
L arge W /L ’s
H igh er C ap acitan ce
L ow er V oltage
Larger sized devices are useful only when interconnect dom inated.
M in im u m sized d evices are u su ally op tim al for low -p ow er.
Digital Integrated Circuits
Low Power Design
© Prentice Hall 1995
Transistor Sizing for Fixed Throughput
Cg = W/L CMIN
I  W/L CMIN
C MIN = Minimum sized gate (W/L=1)
W /L after sizing
CP = Cwiring + CDF
 = CP / (K CMIN)
HIGH PERFORMANCE
W/L >> CP / (K C MIN)
LOW POWER
W/L  2 CP / (K C MIN)
(if C P K C MIN)
ELSE W/L = 1
N O RM A LIZ E D E NE RG Y
10
7
 =0
5
4
= 0.5
3
2
=1
1.5
adder
1.0
0.7
 = 1.5
=2
0.5
1
3
10
W/L
Digital Integrated Circuits
Low Power Design
© Prentice Hall 1995
Reducing Effective Capacitance
L ocal bus architecture
G lobal bus architecture
S har ed R e sour ce s inc ur Sw itc hing O ve rh ead
Digital Integrated Circuits
Low Power Design
© Prentice Hall 1995
Summary
• Pow er D iss ip ation is be com ing P r im e D e sign
C onstr aint
• L ow P ow e r D es ign re qu ir e s O ptim iz ation at all L e vels
• Sour c es of Pow er D iss ip ation are w e ll c har ac te r iz e d
• L ow P ow e r D es ign re qu ir e s ope r ation at low es t
pos sible voltage and c lock spe e d
Digital Integrated Circuits
Low Power Design
© Prentice Hall 1995
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