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JPS5235244

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DESCRIPTION JPS5235244
■ Stereo matrix circuit [stock] Tokisho 46-38867 [Phase] Application Akira 46 (1971) June 2
published Shiro 48-6701 @ Sho 48 (1973) January 27 @ inventor Nakahiro Satoshi Kamon
Shinichi Ogata Kamon 1006 Matsushita Electric Industrial Co., Ltd. Uchida Yamada Harubo
Dosho (C) Applicant Matsushita Electric Industrial Co., Ltd. Kadoma City Oji Kamon Shin 1006 It
is an object of the present invention to provide an apparatus capable of matching the
characteristics of left and right separation. FIG. 1 shows a conventional stereo matrix circuit,
which is used, for example, in a sound multiplex stereo matrix of a television receiver, a fourchannel stereo system, and the like. When an L-R signal is input from the signal source 1 and an
L-}-R signal is added from the signal source 2, -L + -R is output to the collector of the transistor 3,
and 2R is obtained at the output terminal 4. Further, L-R is output to the emitter of the transistor
3 and 2L is obtained at the output terminal 5. In this circuit, when adjusting the degree of
separation, -R is inserted into the signal source 1 and R is inserted into the signal source 2. Then,
the variable resistor 6 is adjusted so that the output of the terminal 5 becomes zero. Next, L is
applied to the signal sources 1 and 2 and the variable resistor 6 is adjusted so that the output of
the terminal 4 becomes O. Then, the adjustment for R will be completed, and it is impossible to
adjust the degree of separation satisfying both R and L. The present invention is intended to be
able to adjust the degree of separation for both R and L, and one embodiment of the present
invention will be described below with reference to the drawings. As shown in FIG. 2, the
collectors of the transistors 7 and 8 are connected to each other, to which a B voltage is applied
via a resistor and an output terminal 9 is provided. Further, the collectors of the transistors 10
and 11 are connected to each other, to which a B voltage is applied via a resistor and an output
terminal 12 is provided. The transistors 8 and 100 bases are directly connected, and an L-1-H
signal source 13 is connected thereto via a capacitor 14. An L-R signal source 17 is connected to
the base of the transistor 7 via a condenser f 15 and a town change resistor 16. The emitter of
the transistor 75 is connected to the emitter of the transistor 11 via a resistor 18. The emitters of
the transistors 8 and 11 are grounded via a resistor 19.20 [111111] EndPage: 1, and the emitter
of the transistor 10 is grounded via a variable resistor 21. A fixed bias circuit consisting of
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resistors 22 and 23 is connected to the base of the transistor 110.
When an L-R signal is applied to the signal source 17 and an L-1-R signal is applied to the signal
source 13, the signals -L + R and -L-H appear at the collectors of the transistors 7 and 8, both are
added, and the output is output. A signal of -2L is outputted to the terminal 9. On the other hand,
-L-R and L-R appear at the collectors of the transistors 10 and 11, and -2R appears at the output
terminal 12. When adjusting the degree of separation, add -R to the signal source 17 and R to the
signal source 13. Then, the variable resistor 16 is adjusted so that the output of the terminal 9
becomes zero. Next, L is added to both signal sources 17.13, and the town variable resistor 21 is
adjusted to control the gain of the transistor 10 so that the output of the terminal 12 becomes O.
Thus, left and right separation adjustments can be made independently by the variable resistors
16 and 21. FIG. 3 shows the degree of separation of the circuits of FIGS. 1 and 2. a and b are
those of FIG. 1 and C is that of FIG. 2, and the characteristics are the same. As described above,
according to the present invention, the degree of separation between the left and right can be
adjusted by w4444- + 11, and can be adjusted to the best state. In addition, the circuit can be
configured as a direct connection type with a transistor and a resistor, and integration can be
easily achieved. Furthermore, since the fourth transistor 11 obtains a signal from the emitter of
the first transistor 7, there is no need to invert the polarity of the signal 17 and add it to the base
of the fourth transistor 11, and the circuit is not complicated. is there.
BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a circuit diagram of a conventional stereo
matrix circuit, FIG. 2 is a circuit diagram of a stereo matrix circuit according to an embodiment of
the present invention, and FIG. 3 is a circuit diagram of FIGS. FIG. 7.8.10.11 · · · · · · · · · · · · · · · · · · ·
· · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · signal source Resistor 9, 12 ...
output terminal 18 ... resistance. [Phase] Citation of Japanese Patent Publication No. 41-15317
[111111] EndPage: 2
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