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JPS5143101

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DESCRIPTION JPS5143101
BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing an embodiment of a
four-channel stereo demodulation circuit according to the present invention, and FIG. 2 is a
specific circuit connection diagram thereof. 3 ... PLL, 4 ... synchronous detection circuit, 9 ... high
speed muting circuit connection pin, 10 ... high speed muting circuit, 13 ... input signal display
device. Oh / river i-real opening 5l-43101 (2) one day 2-
[Detailed description of the invention] In this affair, according to the demodulator circuit of the
four product serialized nayanoiru stereo equipped with a human power signal surface E device,
in the number, provide # # / / dedicated to the display color d The present invention relates to a
4-channel stereo 11) stereo demodulation device which has superior display of an input signal by
utilizing non-use of existing bits / without other functions. The connection bin is extracted for
each function in the well-integrated integrated circuit 94 channel demodulator, and the abovementioned human power v display circuit is also dedicated to it. It was connected to t & t bel /.
However, in the case of 2 as well, bins are output for each function from the collection circuit,
and the number of pins increases as the number of pins increases. Therefore, the circuit is also
complicated, and there is a disadvantage that the cost increases and the yield decreases.
Integrate p1 into this device; # l! Q) To reduce the number and to reduce the cost and to improve
the yield by 1 =]. . That is, in the case of the action-type collar having a diver's 9th connection,
this bi / sick person's power signal table non-circuit is connected by using a bin for the nonhistory, and the above-mentioned The signal front cover device is operated. In the following,
detailed description will be made in detail by referring to FIG. FIG. 1 is a block diagram of a 4channel / channel stereo demodulator according to one embodiment of the present invention.
The input terminal (bin) II11c is supplied to the modulated FM difference signal which is a
human power signal at-, and the automatic gain control circuit (the bond whose carrier level is
equalized at 21, phase loop group (PLL) + 31 and synchronous detection @ (Add to 41. In the
PLL 131, phase synchronization is achieved with a human power signal and a signal of a
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frequency coincident with a bond input signal generated from a voltage controlled oscillator with
a frequency of 5 rca. iやL−cいヵ、! 9え−よ、えイ、。。 The 1.5.sup.th (.sup.k) period
detection circuit 141 [@ supplied-The human power signal supplied to the PLL 131 is
transmitted to the '4i equalize 5 ther 16) via the bin (5). The synchronization detection circuit 4)
multiplies the synchronization signal with the input signal, and one output of the detection circuit
is specified as an automatic interest rate control cycle I @ 2 + 1'C while being bin dust 7). AGe
filter 81 will be supplied via the other 10,000 outputs, ie the field outside through the annealing
signal nihin (9)! l! It is supplied to the 4th muting circuit 1 '+ 9 which is l @. When the PLL
131 is locked, the synchronous detection output generated in the bin 19) is maximized, and is
reduced to 31 in the case of the loss of lock.
On the other hand, at pin 17), riPLL + al is out of lock state 1 and is reduced when the one-time
detection output is maximally locked. If PLL 131 loses lock, the output generated in bin 191 is
low as described above, and this output is inverted by high-speed muting circuit 1 (inverter Qll of
I, and the inverted signal causes FI! The iT is turned on to short-circuit the output of the equalizer
+61 in an alternating current. When the to-input difference signal disappears or the one-man
condition becomes transiently abnormal and the PLL 131 loses lock, an abnormal noise occurs in
the detection output, so a high-speed muting circuit ff mini is provided for the purpose of
removing this. There is. Therefore, only when there is no input difference signal or abnormality
occurs in this high speed muting circuit 0 ···, in other words, the lock of PLL 131 is unlocked, ", m
bin for speed connecting circuit) 9) 低 output is low It is used only when it is in the jin jji, i di
level, and it is not used at all in other periods. Therefore, by using this high-speed navigation
circuit connecting bin 19) as a bin for an input signal display device, for example, if a large force
signal 41 display assembly II 3 including an indicator light 1 is lided, non-recording speed
muting circuit This indicator can be illuminated during this period, ie when the input difference
signal is present normally. In other words, there is no need to provide a new connection pin for
the display device. FIG. 11E2 shows a specific connection diagram of the synchronous detection
circuit and the manual power signal display device of the 4-channel stereo demodulator
according to the present invention. C in the figure? Reference numeral 11 denotes a
synchronous' detection circuit, which is an integrated circuit f9. This synchronous detection
circuit Q! A first differential transistor pair Q1. It is composed of Q2, a second differential
transistor pair Qs, Qa and a third differential pair differential transistor AQj, Q6, and a person! A
modulated difference signal, which is a free input, is supplied to the base of the transistors Qs
and Qs, and is supplied to the base of the transistor QzA-b as the 1If1 period signal from PI, l.
When the modulated differential signal and the synchronous bias are in phase synchronization as
shown in the figure, in the negative half cycle (positive half cycle of the temporary modulated
differential signal) of the synchronous double angle, the transistors Qak and Q @ 44 (A current
flows in the 51 transmission path of the transistor Q4 + the transistor Q6 of the AuC filter from
the power supply S'cc, and the positive half of the sync signal (l correction-,, 'negative half cycle
of the modulated difference signal And the transistors Q2 and Qs are turned on, and a current
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flows from the power supply ˜ 'cc through the AGO filter, the transistor Q2 and the transistorprovided shoulder path.
That is, when the 1th I phase synchronization is achieved and there is a single character, the
current flowing from the power supply − 'cc to the transistor Q1 or Q3 via the resistor IIL1 is rl
(and thus the resistor R1,! :) The potential of the high-speed muting circuit connection bin
connected to the connection point with the Qz collector is kept high. However, if a difference
occurs in the modulated difference signal, and if the difference between the modulated signal and
the shift signal does not occur, or if the q-phase synchronization between the mouth and key and
the sync signal is shifted, the sync signal is positive or negative. In the cycle VC sequin l, the
resistance element l starts to flow, so it drops to the potential of Hinko. At this time, it operates
on the high speed muting circuit connected to Hin and works to attenuate the detection output.
The input signal display device is connected to the above-mentioned pin taK as = l + s. A
transistor (龜!) That switches as a base input the signal generated by this signal. I / Q7 is
connected. A lamp is connected to the collector 1 cover of the transistor Q7 and supplied with 1
@ S'cc1N. In addition, the emitter is superior through a resistor R3 and through a 4Km resistance
when it is turned on by a distributed power supply X'ccKm. When the output of the pin mouth is
at bird level, in other words when the PLL is locked [il 1mL lamp (turning on), the input layer
signal is normally supplied, 1 It informs that 4 channels recovery 1IIIIJ work is row rx, and
conversely, when PLL output falls out and the output of binm becomes low h, 消 灯 / no (至)
extinguishes, 4 channels recovery WJ4 ! I! Informs that one work has not been done.
However, the level difference between the high level and the low level of the output generated in
the hinta is small, which causes the flickering of the lap to give rise to a malfunction. Therefore,
methods such as amplifying the output and adding the transistor Q7K, increasing the power
supply voltage Vcc to hk'f, increasing the value of the resistance R, etc. can also be overcome, but
they are not OT capable in collecting circuit design etc. Since neither of them is undesirable for
the reason, the resistor R1 + 71 and the transistor Q1. There is a method of providing a transistor
with a current-to-earth connection through resistor B2 from the point of Ii connection with the
collector of Qs, and adding an i-neeting signal present in the demodulation circuit to the pace of
this transistor Qm to switch it. It is used. That is, when the i-kneading signal is applied, the
transistor false becomes conductive, and from the power supply ˜ 'cc, the charge R becomes the
transistor Q1.
Not only flows to Qs, but also resistance island, transistor! It flows through-. That is, the current
flowing through the resistor at increases, and the collector potential of the transistors Q * and Qs
decreases accordingly. If the level difference between the high and low levels of the bin OK
generated is made large enough to switch the transistor Q1, .quadrature. Can be obtained.
According to this method, I @ does not occur between integrated circuits in integrated circuit
design without any interference with the operation of the synchronous detection circuit. In the
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above example, the input signal display device was operated using the high speed blinding bin
(C) together, but for example, the pin for AGO filter also has the shape 11 of the human power
difference signal (PLL is locked Such bins can be used in combination with the input signal
display as described above, as they are or are not used depending on the case (8) r (if yes). As
described above, according to the present invention, an existing signal processing unit is used in
combination with an existing bin which is not used in an operating state of the integrated circuit,
and an input signal display unit is connected to this and the unused period of the above bin It is
not necessary to provide a connection bin dedicated to the input signal display device in advance.
Therefore, it is possible to achieve the reduction of the number of bins, the reduction of the chip
surface structure, the wandering of the circuit, the cost reduction, the same as the step 111Q,
and it is possible to provide a four channel stereo demodulator useful practically. .
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