вход по аккаунту


код для вставкиСкачать
Patent Translate
Powered by EPO and Google
This translation is machine-generated. It cannot be guaranteed that it is intelligible, accurate,
complete, reliable or fit for specific purposes. Critical decisions, such as commercially relevant or
financial decisions, should not be based on machine-translation output.
BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a basic block diagram of the present invention,
and FIG. 2 is a connection diagram of an embodiment of the present invention. Reference
numeral 1L denotes a terminal to which the left signal is supplied, 1R denotes a terminal to
which the right signal is supplied, 4L, 4R, 8L, 8R, and detectors SL and 5R for AGC. Fig. 1-107Judo 50-4 · 60 · 43 (2) Fig. 2-ios-
Detailed description of the invention This l # lI is an abbreviation of AGC @ applied to the
automatic recording circuit of the keypres, DAC, AGC times of stereo signal in the register 'IIc
111 f 4 ° AGCd 従 来 of conventional stereo signal, left IC And the output of the right signal is
rectified by -mt, and one capacitor VC is collected to obtain the common sensor voltage of the left
and right channels (11 channel circuit 1114 circuit). In this way, 1 channel signal 1 degree
becomes identical to 1 j [1 word] by the 4t-equally 111 m-t; b ξ of both channels, and the sense
of stereo is never customary T 'L 43. However, in the case of submersible AGC1, it is necessary to
learn the operation start time required for AGO-I to operate after the input signal is received, and
input / deletion 4 * to 1iI11 slow t Me when Shofuku to 1 until 4 to be borrowed recovery ... to
Mom, - ten thousand when the pulse-like Daiki input signal to the D channel g & is admonished
No. 1 of the other channel 舗必VCfgl 倭 倭 欠 点 欠 点 欠 点 欠 点 欠 点 欠 点 欠 点 欠 点 欠 点 考
案 考 案 考 案 考 案 考 案 本 本 本 本 AGC AGC AGC AGC h h h s 図 s s は は s は QC QC AQC
circuit by The basic configuration is shown, and in (15), (IL) indicates the left signal h of the
stereo signal (indicates n representing one thousand denominations-one (1)) indicates that the
right signal is provided and the f 'L61 child. These left 1 and right 1 are respectively 眞 λ
amplification! I (2 L) (I B) び 増 友 (3 L) (3)) to be supplied to the load via f L and left
compensation + 21 and right 1-4 spray device (4 L) (Lead to 41 (). Also, on the left channel of the
front amplification = ii (2 L) and the post-stage amplifier (3 L), the rumor 4111 wholesaler is
available, and the fAGc 4 transistor (51,) 4 is provided. But the transistor (5R) for 4+ 'CpLGC is iff
et al. The emitters of the transistors (5L) and (5R) for the AQC and the like are grounded (the
mirror is grounded to the respective channels via capacitors (6L) and (6). The transistor (5L) (5L)
is formed at the base of the transistor (5L) (5L) by 1rL7 formed by detection a (4L) (4L) through
the voltage voltage; each diode (7L) L full), transistor (5L) (51%) Koreri ・ Emitter 1 ■
Impedance is changed, this is the amount of attenuation of the Eri left signal and the right signal!
The control is 1 and the amplification in (2L) (3i,) and (2K) (3FL) are s1 # 1 heart. 自己 6AQCtri
と 同 嫌 こ の 自己 A 6 AQCtri 未 こ の 咋 咋 咋 カ カ カ カ カ 0, 0, 0, 0, 0, 0, 0, (((((((故 故, *
Compensation 'a (4L) (4B) charge / discharge time constant is selected and 9% to t% after λ
Partial t-injection (31 Ji 5 (8 L) l 'c 倶 ML, left side of the left signal from (31,), check 1 l [p (81,)]
VEL 1 n 7 tll wholesale voltage 會 diode (9 L) through the right channel Apply to the base of the
transistor (5 kL). On the other hand, a part of the right No. 1 is supplied to the 41 waver (8), and
the left channel D transistor (5L) via the tranjector (8R) via the tt2 WNla voltage t diode (9B).
Give to the base of. Here, 嘴, II! (81,) (8) L) no charge 41 fixed aU1 mfi device (41,) uR) no f 'L yo
is also long, that is, @ l' r-shoulder at the start time Ruru. For example, a long bowl (4L) (4L) is
formed by a control voltage and starts operating with a control voltage. ★ 凄 (81,) (8R) formed
by 憫 n 憫 A pressure cut start waiting wait 15 is 5 seconds (A is determined gold. tt, 噴 虐 (81,)
(81 () 's 1 碍 疋 碍 疋, * L 4 (4 L) (4 R) 噌 噌 噌 口 口 口 口 侍 侍 よ う よ う よ う よ う よ う几, if
you line up, the same 5 橿 degree as in 開 ′ ′ f L j). In the case of the above-mentioned 4111
or the present 4VC, a large I l input signal pulsed to one channel is transmitted to one channel
within 0.1 second or less as in the prior art. However, since the local Nayanne (I / I's traveling for
41 Le, one channel is not affected by the shadow 4 by the 14 VI-like input of this one channel,
the other channel Gain power I I need to suppress more than necessary, the sound is shaken t9
11! ・1い。 ま*、=l! In 1 騎 @ 、, the control channel based on the word of the own
channel, and the wholesale voltage based on the channel word of the local channel are combined
and the part 1, t ,! The pressure is not an A (jC is not a stereo, a confusing A !, a Ji w / f L '. Figure
2 shows a line of Gin II, and Figure 2 shows an output 1 of (IL) 'ML and (1) 1 1 step amplifier, Cl
0 L) (+ OR) indicates that the left signal and part of the right sign are 4If rL4) door opening, (IIL)
(11 le) is 1iIf times 4 (IOL) (lOR) F [nt smoothed times gt -Show. Ko 几 D 鷹 鷹 @ (IOL) CIOR! The
smoothing circuit (IIL) (llft) is also constructed in the same manner. The cliff circuits (IOL) and +4
(b) (llL) correspond to 41 waves @ (41,) in Fig. 11, and the rectifying circuit (10 and smooth (gl
(II)) are scabs!
It corresponds to I (4R). Then, the voltage from the smoothing circuit (IIL) (voltage is applied to
the base of the transistor (51 L (14 L)), and the DC voltage from the smoothing circuit @ (tlf L) is
applied to the base of the transistor (14 R). The diode (12 chickens) (12 L) K is a smoothing
circuit (13 L) of the same structure, respectively, with the diode (12 R) (12 L), the left one word
and the right signal 14 all 11 (133) is connected n. The llI flow pressure from one smoothed path
(13L) is a transistor (1) (16L) and a capacitor (171,) through a parallel change of M (15L) and a
parallel resistance (17,). The 111 pressure of the pre-circuit (13R) of n 6 10,000 is given to the
base of 18L) through the variable resistor (15R ·) and the string (1 nt low resistance 16B) and the
capacitor (17B) and the transistor (2) Given to the base of 18R). Diode (12 L), smooth 1. gl road
(13 L input j T honey resistance Ll 5 L), 壕 侃 (16 L) and Condena (17 L) ki * lall Kw Ke 6
injection 12 [i! L8L) ic [fiL, diode (12 几), flat fIIl! l! L 烙 L 131 (), variable resistance (15
fields, resistance L 16) 41, and a capacitor (171 'L) hit the bellflower easily (8 cm). And collectors
and emitters of the transistors (14L) and (18) are respectively 4m hard-5n, emitter 6) left 4
common from 4 common point and left 54- formed from a negative waterfall and a right, a right
Depending on the shape · na naKR4, pressure and 'hS mixed E control all E king or n heart out.
Similarly, the emitters of the transistors (14I () and (18L) from the junction point a) are formed
by the right signal and the nt I current voltage voltage signal at 1 説 t1) 1 pressure Control will
be stored. Out of the emitter common connection point of the transistors (14L) and (18) L '! The
'Lt label voltage is given to the base of the left channel AtjC transistor (5L) via a distortion
compensation loop (191,) and a safety diode (201,). The diode (201,) is a 4t device that improves
the base tJK-to-f change of the collector-emitter impedance of the transistor (5L), and the
distortion correction circuit (f9L) is the transistor (5L) & diode (20L) The distortion caused by IC
is to be corrected by t-correction, and the emitter common to the transistors (14R) and (18L) is
also the same as h43 °! In this case, the 9 W control voltage is applied to the base of the right
channel NGC transistor (5 fL) through the 4 W 8 circuit (19 几) word diode (201 (201)).
(7) One 41 examples of this liIura of water supply · (In the case of the self-channel No. 1 level t
control voltage smoothed! (IIL) & (11 IL) f'L intuition. Therefore, Qin Qing! (IIL) and (ttR) (for
DyFy (21L) and (21L): :) light j1 error rate hf, No. 1 is input and then 6 AGC of the transistor (51,)
(5fL) Operation starts. As 1 and the start time of 4 and 1 become less than O9 5 seconds, 1 of
each element of the smoothing circuits (IIL) and (11) is 6 ° for A, Conde yv (21 L) and (21 R) J)
v 4 fixed bit is the input impedance −h! Of the transistor (t 4 L) (t 4 a) of the emitter follower 4
stage. Because it is large, it will be eaten and it will be 擾 、 凹 凹 凹 侍 く な る く な る く な る.
Depending on the signal level of the pond channel q1 tlj + wholesale voltage, 1, smoothed 4 (13
LH 13), then history variable resistance (15 L) (15 L), resistance (16 L) (16 R) and condensation (
17 L) (1 full) time constant times formed by V & over the first time, the recommendation FA start
threshold is delayed to 5 seconds. Depending on the signal level of this other channel, 8 GC's l1 ·
temple by voltage 7t1llJn, during the condensing (l 71. ) (171 () in parallel with resistance (16 L)
(16 K) & variable resistance 18) (15 L) (15 B)-M inserted faster by nh 1 for example 5 seconds
substantially equal to the start 11 It is self-made by S degree. Therefore, according to one
embodiment of the present invention, without using the WN, the wording of one channel is made
smaller than necessary due to the pulsating input of one channel. The sound can be prevented
from being distorted. In one or more explanations, it is preferable to use the A (jc transistor (sL)
(SR) for convenience t ≠ !, and as the gain control means, the bias change of the transistor KF4
gain adjustment means 1. 変 化 を ■ ■ 笥 笥 笥 笥 図 図 図 図 図 図 図 図 図 図 図 図 図 図 図 図
図 図 図 図 図 図 図 図 図 図 図 図 図 図 図 図 図 図 Figure 1 is the basic configuration of the
present invention, Figure 12 is a real result of the present invention 6Js in 4 @ hard row of rows.
(IL) is one signal to which the left signal is supplied, (04) is the signal of the right signal f'L gold,
one child, (41,) (4fL) (8L) (8R) is an autopsy, (5L) (58) A transistor for F ′ i AGC. Utility model
Brass out-People 2-Stock gold company 代 人 藝 = ll = (9) Ritsu-龜 1 '") N? 寞 藝 雫 d!
1! ゞ%-Jl, Cx-1 di 1 ((1 to live to 璽 ・) · · 簀 匈 簀 匈 t-two F-----1 yo face-ff wa-mi % IQQ: $$ 1
ward 0-Saju 9-1 to 舅 pigeon -6, applicants other than the above, utility model registration
applicants or agents (1) inventor yv dakura self I address ( Address) Kanagawa Atsugi-shi Oka m1
family 64-1 Name & Su 7 Address (resident) Name Address (resident) Name Address (resident)
Name Address (resident) Name (2) Utility model registration applicant address (resident) name
(name) 1 register) S address (location) name (name) (nationality) (3) agent
Пожаловаться на содержимое документа