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JP2016123041

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DESCRIPTION JP2016123041
Abstract: The present invention provides an electronic device capable of detecting whether a
three-pole plug or a four-pole plug is inserted in an earphone jack shared by a three-pole plug
and a four-pole plug. A terminal A and a terminal A 'of an earphone jack 12 are connected to a
left audio terminal (L) of a three-pole plug or a four-pole plug, and a terminal B of the earphone
jack 12 is a three-pole plug or By detecting whether it is connected to the right voice terminal (R)
of the 4-pole plug, it is determined whether the 3-pole plug or the 4-pole plug is completely
inserted in the earphone jack 12. [Selected figure] Figure 14
Electronics
[0001]
The present invention relates to an electronic device.
[0002]
Conventionally, a device is known that can identify which one of a plurality of types of earphone
plugs has been inserted into an earphone jack.
[0003]
For example, mobile phones equipped with a 5-pole earphone jack shared by a 4-pole plug and a
5-pole plug are known.
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The 4-pole plug transmits a microphone signal, a left audio signal, a right audio signal, and a
ground voltage, and the 5-pole plug transmits a PTT switch signal, a microphone signal, a left
audio signal, a right audio signal, and a ground voltage.
[0004]
When the plug is inserted, a tone signal is output from the third jack terminal.
At this time, if the 4-pole plug is inserted, the tone signal is output as a leak signal from the first
jack terminal via the 4-pole earphone, and the leak signal is input to the control circuit after
being amplified. On the other hand, when the 5-pole plug is inserted, the leak signal is not
output. Such a configuration makes it possible to identify which one of the 4-pole plug and 5pole plug has been inserted.
[0005]
JP, 2013-66149, A
[0006]
By the way, it is necessary to detect whether the 3-pole plug or 4-pole plug is inserted into the
earphone jack shared by the 3-pole plug and the 4-pole plug.
[0007]
Therefore, an object of the present invention is to provide an electronic device capable of
detecting whether a three-pole plug or a four-pole plug is inserted into an earphone jack shared
by the three-pole plug and the four-pole plug.
[0008]
An electronic device according to one embodiment of the present invention includes an earphone
jack connectable to a three-pole plug earphone and a four-pole plug earphone.
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The three-pole plug earphone includes a three-pole plug including a first terminal, a second
terminal, and a third terminal in order from the tip.
The four-pole plug earphone includes a four-pole plug having a first terminal, a second terminal,
a third terminal, and a fourth terminal in order from the tip.
The earphone jack includes a first terminal, a second terminal, a third terminal, a fourth terminal,
and a fifth terminal. The first terminal, the second terminal, the third terminal, the fourth
terminal, and the fifth terminal are arranged in order from the back side on the inner surface of
the plug insertion hole of the earphone jack. The first and second terminals are disposed at
different azimuthal angles on the inner surface. In the electronic device, further, the first terminal
and the second terminal of the earphone jack are connected to the first terminal of the three-pole
plug or the four-pole plug, and the third terminal of the earphone jack is the three-pole plug or
the four-pole plug And a control unit that determines whether or not the three-pole plug or the
four-pole plug is completely inserted in the earphone jack by detecting whether or not it is
connected to the second terminal.
[0009]
According to an aspect of the present invention, it is possible to detect whether a three-pole plug
or a four-pole plug has been inserted into an earphone jack shared by the three-pole plug and the
four-pole plug.
[0010]
It is a figure showing the composition of the personal digital assistant of this embodiment.
It is a figure showing a three-pole plug earphone. It is a figure showing 4 pole plug earphone.
FIG. 5 represents the connection of the components in a three-pole plug earphone. FIG. 4
represents the connection of the components in a four-pole plug earphone. It is a figure showing
the state where a 3 pole plug was completely inserted in an earphone jack. It is a figure for
demonstrating the azimuth on the inner surface of the plug insertion hole of the earphone jack of
terminal A, A ', B, C, D. FIG. It is a figure showing the state where a 4 pole plug was completely
inserted in an earphone jack. It is a figure showing the state where a 4 pole plug was inserted
halfway into an earphone jack. It is a figure showing the state where a 3 pole plug was
completely inserted in an earphone jack. It is a figure showing the state where a 4 pole plug was
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3
completely inserted in an earphone jack. It is a figure showing the state where a 4 pole plug was
inserted halfway into an earphone jack. It is a figure showing the state where the 3-pole plug in
this embodiment was completely inserted in the earphone jack. It is a figure showing the state
where the 4 pole plug in this embodiment was completely inserted in the earphone jack. It is a
figure showing the state where the 4-pole plug in this embodiment was inserted halfway into an
earphone jack. It is a flowchart showing the procedure of plug insertion / removal determination,
plug type identification, and setting identification of a momentary switch.
[0011]
Below, it demonstrates using portable terminals, such as a smart phone, as one form of an
electronic device. (Configuration of Portable Terminal) FIG. 1 is a diagram showing a
configuration of portable terminal 1 according to the present embodiment.
[0012]
Referring to FIG. 1, the portable terminal 1 includes a CPU (Central Processing Unit) 2, an
antenna 61, a microphone 62, a speaker 63, a key input unit 64, a display 65, a memory 66, and
a voltage setting unit. And an audio processing unit 3 and an earphone jack 12.
[0013]
The earphone jack 12 is connectable to the three-pole plug earphone 91 and the four-pole plug
earphone 92.
[0014]
The voltage setting unit 154 is provided for the insertion / removal state of the three-pole plug
earphone 91 and the four-pole plug earphone 92 in the earphone jack 12 and for identifying
whether the type of the inserted earphone is three or four.
Details will be described later.
[0015]
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The CPU 2 performs overall control.
The antenna 61 transmits and receives radio signals to and from the radio base station.
[0016]
The key input unit 64 is configured by a touch panel or the like, and receives an input from the
user. The display 65 displays an image sent from the CPU 2.
[0017]
The memory 66 stores various data. The audio processing unit 3 outputs an audio signal to the
speaker 63 and receives an audio signal from the microphone 62 when the earphone is not
inserted into the earphone jack 12. The audio processing unit 3 outputs an audio signal to the
three-pole plug earphone 91 when the three-pole plug earphone 91 is inserted in the earphone
jack 12. The audio processing unit 3 outputs an audio signal to the four-pole plug earphone 92
and receives an audio signal from the four-pole plug earphone 92 when the four-pole plug
earphone 92 is inserted in the earphone jack 12.
[0018]
The microphone 62 outputs the input audio signal to the audio processing unit 3. The speaker
63 reproduces the audio signal sent from the audio processing unit 3.
[0019]
(Structure of Earphone) FIG. 2 is a diagram showing a three-pole plug earphone 91. As shown in
FIG.
[0020]
The three-pole plug earphone 91 includes a three-pole plug 51, a silicone cap 13a for the left ear,
a housing 16a and a speaker 17a, a silicone cap 13b for the right ear, a housing 16b and a
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loudspeaker 17b.
[0021]
FIG. 3 is a diagram showing the four-pole plug earphone 92. As shown in FIG.
The four-pole plug earphone 92 includes a four-pole plug 52, a microphone 28, a momentary
switch 161, a silicone cap 23a for the left ear, a housing 26a, a speaker 27a, a silicone cap 23b
for the right ear, a housing 26b, and And a speaker 27b.
[0022]
When the momentary switch 161 is turned on, mute processing, disconnection of a voice call,
reproduction of music data, or stop of music data are performed.
[0023]
(Connection Relationship Between Components in Earphone) FIG. 4 is a diagram showing
connection of components in three-pole plug earphone 91. Referring to FIG.
[0024]
The three-pole plug 51 is a plug conforming to the EIAJ (Electronic Industries Association of
Japan) standard.
The diameter of the three-pole plug 51 is 3.5 mm.
The three-pole plug 51 includes a left audio terminal (L) (first terminal), a right audio terminal (R)
(second terminal), and a ground terminal (GND) (third terminal) in order from the tip.
The portions shown in black in FIG. 3 are made of an insulator.
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[0025]
The speaker 17a has an input terminal 95a and a voltage input terminal (ground terminal) 96a
for the ground. The speaker 17 b has an input terminal 95 b and a voltage input terminal
(ground terminal) 96 b for the ground.
[0026]
The left audio terminal (L) is connected to the input terminal 95a of the speaker 17a. The right
audio terminal (R) is connected to the input terminal 95b of the speaker 17b. The ground
terminal (GND) is connected to the ground terminal 96a of the speaker 17a and the ground
terminal 96b of the speaker 17b.
[0027]
FIG. 5 is a diagram showing connection of components in four-pole plug earphone 92. Referring
to FIG. The four-pole plug 52 is a plug conforming to the EIAJ standard. The diameter of the fourpole plug 52 is 3.5 mm. In addition, the signal arrangement of the four-pole plug 52 conforms to
the Cellular Telephone Industry Association (CTIA). The four-pole plug 52 has a left audio
terminal (L) (first terminal), a right audio terminal (R) (second terminal), a ground terminal (GND)
(third terminal), and a microphone terminal in order from the tip. (M) (fourth terminal)
[0028]
The speaker 27a has an input terminal 71a and a voltage input terminal (ground terminal) 72a
for ground. The speaker 27 b has an input terminal 71 b and a voltage input terminal (ground
terminal) 72 b for grounding. The microphone 28 has an output terminal 74 and a voltage input
terminal (ground terminal) 73 for ground.
[0029]
The left audio terminal (L) is connected to the input terminal 71a of the speaker 27a. The right
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audio terminal (R) is connected to the input terminal 71b of the speaker 27b. The ground
terminal (GND) is connected to the ground terminal 72a of the speaker 27a, the ground terminal
72b of the speaker 27b, and the ground terminal 73 of the microphone 28. The microphone
terminal (M) is connected to the output terminal 74 of the microphone 28.
[0030]
A momentary switch 161 shown in FIG. 3 is provided between the output terminal 74 of the
microphone 28 and the ground terminal 73 of the microphone 29. When the momentary switch
161 is set to ON by the operation of the user, the output terminal 74 of the microphone 28 and
the ground terminal 73 of the microphone 29 are connected.
[0031]
Next, the positional relationship between the terminal of the earphone jack 12 and the terminal
of the three-pole plug and the terminal of the four-pole plug will be described.
[0032]
FIG. 6 is a diagram showing a state in which three-pole plug 51 is completely inserted into
earphone jack 12.
[0033]
As shown in FIG. 6, from the back side on the inner surface of the plug insertion hole of the
earphone jack 12, the terminal A '(DET) (first terminal), the terminal A (LCH) (second terminal),
the terminal B (terminal RCH) (third terminal), terminal C (GND) (fourth terminal), and terminal D
(MIC) (fifth terminal) are arranged.
[0034]
FIG. 7 is a view for explaining an azimuth on the inner surface of the plug insertion hole of the
earphone jack 12 of the terminals A, A ′, B, C, D.
[0035]
FIG. 7A is a cross-sectional view taken along the line I-I 'of the plug insertion hole shown in FIG.
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The terminal A ′ (DET) is disposed at an azimuth of 90 ° on the inner surface of the plug
insertion hole radius r1.
[0036]
The terminal A (LCH) is disposed at an azimuth angle of 180 ° on the inner surface of the plug
insertion hole radius r1.
[0037]
FIG. 7B is a cross-sectional view taken along the line II-II ′ of the plug insertion hole shown in
FIG.
The terminal B (RCH) is disposed at an azimuth angle of 0 ° on the inner surface of the plug
insertion hole radius r2.
ただし、r2>r1である。
[0038]
FIG. 7C is a cross-sectional view taken along the line III-III ′ of the plug insertion hole shown in
FIG.
The terminal C (GND) is disposed at an azimuth of 0 ° on the inner surface of the plug insertion
hole radius r2.
[0039]
FIG. 7D is a cross-sectional view taken along line IV-IV ′ of the plug insertion hole shown in FIG.
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The terminal D (MIC) is disposed at an azimuth angle of 180 ° on the inner surface of the plug
insertion hole radius r2.
[0040]
Again referring to FIG. 6, when the three-pole plug 51 is completely inserted into the earphone
jack 12, the three-pole plug 51 is connected to the earphone jack 12 as follows.
[0041]
The left audio terminal (L) is connected to the terminal A (LCH) and the terminal A '(DET).
The right audio terminal (R) is connected to terminal B (RCH). The ground terminal (G) is
connected to the terminal C (GND) and the terminal D (MIC).
[0042]
FIG. 8 is a diagram showing a state in which four-pole plug 52 is completely inserted into
earphone jack 12.
[0043]
When the four-pole plug 52 is completely inserted into the earphone jack 12, the four-pole plug
52 is connected to the earphone jack 12 as follows.
[0044]
The left audio terminal (L) is connected to the terminal A (LCH) and the terminal A '(DET).
The right audio terminal (R) is connected to terminal B (RCH).
The ground terminal (G) is connected to the terminal C (GND). Connect the microphone terminal
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10
(M) to the terminal D (MIC).
[0045]
FIG. 9 is a diagram showing a state in which four-pole plug 52 is partially inserted into earphone
jack 12.
[0046]
In this state, the four-pole plug 52 is connected to the earphone jack 12 as follows.
The left audio terminal (L) is connected to the terminal B (RCH) in addition to the terminal A
(LCH) and the terminal A ′ (DET). The right audio terminal (R) is connected to the terminal C
(GND). The ground terminal (G) is connected to the terminal D (MIC). The microphone terminal
(M) is not connected to any terminal.
[0047]
Next, a method relating to the exchange of signals with the earphone in the portable terminal 1
will be described. FIG. 10 is a diagram showing a state in which three-pole plug 51 is completely
inserted into earphone jack 12.
[0048]
The audio processing unit 3 includes a microphone audio processing unit 151, a first audio
output unit 152, and a second audio output unit 153.
[0049]
The microphone sound processing unit 151 includes an amplifier 5 and an AD converter 4.
The amplifier 5 is connected to the terminal D (MIC) of the earphone jack 12. The amplifier 5
amplifies the audio signal output from the terminal D (MIC). The AD converter 4 converts the
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11
audio signal output from the amplifier 5 into a digital signal.
[0050]
The first audio output unit 152 includes a DA converter 6 and an amplifier 7. The DA converter 6
converts the digital audio signal for the left ear into an analog audio signal. The amplifier 7
amplifies or attenuates the audio signal output from the DA converter 6. The amplifier 7 is
connected to the terminal A (LCH) of the earphone jack 12.
[0051]
The second audio output unit 153 includes a DA converter 8 and an amplifier 9. The DA
converter 8 converts the digital audio signal for the right ear into an analog audio signal. The
amplifier 9 amplifies or attenuates the audio signal output from the DA converter 8. The
amplifier 9 is connected to the terminal B (RCH) of the earphone jack 12.
[0052]
The voltage setting unit 154 includes a first pull-up resistor R1 (= 100 kΩ), a first pull-down
resistor R2 (= 10 kΩ), an inverter IV, and a ground 155.
[0053]
The first pull-up resistor R1 is provided between the first node ND1 on the wiring between the
terminal A '(DET) of the earphone jack 12 and the CPU 2 and the power supply voltage VDD (= 2
V) for pull-up. Connected
[0054]
The first pull-down resistor R 2 is connected between the second node ND 2 on the wire between
the terminal A (LCH) of the earphone jack 12 and the first audio output unit 152 and the ground
155.
[0055]
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12
The inverter IV inverts the voltage of the fourth node ND3.
The ground 155 is connected to the terminal C (GND) of the earphone jack 12.
[0056]
The CPU 2 has a GPIO (General Purpose Input / Output) interface 11.
The GPIO interface 11 has terminals GPIO̲0 and GPIO̲1.
[0057]
The terminal GPIO̲0 is connected to the first node ND1.
The CPU 2 receives the detection signal DET input to the terminal GPIO̲0.
[0058]
The terminal GPIO̲1 is connected to the output of the inverter IV. The CPU 2 receives the signal
Mic̲SW input to the terminal GPIO̲1.
[0059]
The speaker 17a connected between the left voice terminal (L) and the ground terminal (G) of the
three-pole plug 51 is represented by a resistance RX (= 8 Ω) when represented by an
equalization circuit. The speaker 17 b connected between the right audio terminal (R) and the
ground terminal (G) of the three-pole plug 51 is represented by a resistor RY (= 8 Ω) when
represented by an equalizing circuit.
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13
[0060]
As shown in FIG. 10, when three-pole plug 51 is completely inserted into earphone jack 12, first
node ND1 is connected to power supply voltage VDD via first pull-up resistor R1 (= 100 kΩ). ,
Terminal A '(DET), left audio terminal (L), terminal A (LCH), and first pull-down resistor R2 (= 10
k.OMEGA.) To ground 155, terminal A' (DET), left audio terminal (L), resistor RX (= 8Ω), ground
terminal (G), and terminal C (GND) are connected to ground 155. Since the value of the resistor
RX is small, the voltage of the first node ND1 is pulled down to the low level (L), and the
detection signal DET input to GPIO̲0 becomes the low level (L).
[0061]
When the detection signal DET changes from high level (H) to low level (L), it is determined that
any plug is completely inserted into the earphone jack 12, and the type of the inserted plug is
determined as follows. .
[0062]
The fourth node ND3 is connected to the ground 155 through the terminal D (MIC) and the grant
terminal (G), and thus becomes the low level (L).
As a result, the signal Mic̲SW input to GPIO̲1 via the inverter IV becomes high level (H). The
CPU 2 determines that the plug inserted in the earphone jack 12 is the three-pole plug 51 by
detecting that the signal Mic̲SW is at the high level (H).
[0063]
FIG. 11 shows a state in which four-pole plug 52 is completely inserted into earphone jack 12.
[0064]
The speaker 27a connected between the left voice terminal (L) and the ground terminal (G) of the
four-pole plug 52 is represented by a resistance RX (= 8 Ω) when represented by an equalization
circuit.
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14
The speaker 27 b connected between the right audio terminal (R) and the ground terminal (G) of
the four-pole plug 52 is represented by a resistor RY (= 8 Ω) when represented by an equalizing
circuit.
[0065]
As shown in FIG. 11, when the four-pole plug 52 is completely inserted into the earphone jack
12, as in the case where the three-pole plug 51 is completely inserted into the earphone jack 12,
the first node ND1 Terminal A '(DET), left audio terminal (L), terminal A (LCH), first pull-down
resistor R2 (= 10 kΩ), connected to the power supply voltage VDD through one pull-up resistor
R1 (= 100 kΩ) Through the terminal A '(DET), the left audio terminal (L), the resistor RX (= 8
.OMEGA.), The ground terminal (G), and the terminal C (GND). . Since the value of the resistor RX
is small, the voltage of the first node ND1 is pulled down to the low level (L), and the detection
signal DET input to GPIO̲0 becomes the low level (L).
[0066]
When the detection signal DET changes from high level (H) to low level (L), it is determined that
any plug is completely inserted into the earphone jack 12, and the type of the inserted plug is
determined as follows. .
[0067]
The fourth node ND3 is connected to the microphone terminal (M) via the terminal D (MIC), and
thus becomes high level (H).
As a result, the signal Mic̲SW input to GPIO̲1 via the inverter IV becomes low level (L). The CPU
2 determines that the plug inserted in the earphone jack 12 is the four-pole plug 52 by detecting
that the signal Mic̲SW is at the low level (L).
[0068]
When it is determined that the plug inserted in the earphone jack 12 is the four-pole plug 52,
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15
while the detection signal DET is at low level (L), whether or not the momentary switch 161 is set
to ON is determined by the voltage level of the signal Mic̲SW. It is judged. When the momentary
switch 161 is set to ON, the microphone terminal (M) and the ground terminal (G) are connected.
As a result, the terminal D (MIC) is connected to the ground 155 via the microphone terminal
(M), the ground terminal (G), and the terminal C (GND), so that the signal Mic̲SW becomes high
level (H). The CPU 2 determines that the momentary switch 161 is set to ON by detecting that
the signal Mic̲SW is at the high level (H).
[0069]
FIG. 12 is a diagram showing a state in which four pole plug 52 is partially inserted into
earphone jack 12.
[0070]
In this state, the first node ND1 is connected to the power supply voltage VDD through the first
pull-up resistor R1 (= 100 kΩ), and the terminal A ′ (DET), the left audio terminal (L), the
terminal A (LCH) ), The first pull-down resistor R2 (= 10 kΩ) is connected to the ground 155.
Furthermore, the first node ND1 is connected to the second audio output unit 153 via the
terminal A ′ (DET), the left audio terminal (L), and the terminal B (RCH). Since the second audio
output unit 153 does not increase the voltage of the first node ND1, the voltage of the first node
ND1 becomes low level (L), and the detection signal DET input to GPIO̲0 is low level (L L)
[0071]
Since the detection signal DET is set to low level (L), it is erroneously determined that any plug is
completely inserted into the earphone jack 12, and the type of the inserted plug is determined as
follows.
[0072]
The fourth node ND3 is connected to the ground 155 through the terminal D (MIC), the ground
terminal (G), the resistor RY (= 8Ω), the right audio terminal (R), and the terminal C (GND). It
becomes low level (L).
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As a result, the signal Mic̲SW input to GPIO̲1 via the inverter IV becomes high level (H). The
CPU 2 erroneously determines that the plug inserted in the earphone jack 12 is the three-pole
plug 51 by detecting that the signal Mic̲SW is at the high level (H). Further, in FIG. 9, although
the terminal C (GND) is connected to the right audio terminal (R), the terminal C (GND) is located
when the position of the terminal C (GND) is shifted to the left (outside) Sometimes connect with
the ground terminal (G). Also in such a case, the fourth node ND3 is at the low level (L), and the
CPU 2 detects that the signal Mic̲SW is at the high level (H), so that the plug inserted in the
earphone jack 12 is 3 It is misjudged that it is the pole plug 51.
[0073]
Also, if the plug inserted into the earphone jack 12 is correctly determined to be the four-pole
plug 52, if the detection signal DET is set to the low level (L), the momentary switch 161 is set to
ON. It is determined by the voltage level of the signal Mic̲SW. However, in the state of FIG. 12,
even when the momentary switch 161 is off, the terminal D (MIC) is grounded via the ground
terminal (G), the resistor RY, the right audio terminal (R), and the terminal C (GND). And the
signal Mic̲SW becomes high level (H). The CPU 2 erroneously determines that the momentary
switch 161 is set to ON by detecting that the signal Mic̲SW is at the high level (H).
[0074]
In the state where the four-pole plug 12 as shown in FIG. 11 is completely inserted into the
earphone jack 12, the terminal B (RCH) is connected to the right audio terminal (R), while it is as
shown in FIG. When the four-pole plug 12 is partially inserted into the earphone jack 12, the
terminal B (RCH) is connected to the left audio terminal (L). In the schemes shown in FIGS. 11
and 12, such connection differences could not be identified.
[0075]
In the present embodiment, the CPU 2 connects the terminal A '(DET) and the terminal A (LCH) of
the earphone jack 12 to the left audio terminal (L) of the three-pole plug 51 or the four-pole plug
52, and the earphone jack By detecting whether 12 terminals B (RCH) are connected to the right
audio terminal (R) of 3 pole plug 51 or 4 pole plug 52, 3 pole plug 51 or 4 pole plug in earphone
jack 12 It is determined whether 52 is completely inserted.
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17
[0076]
FIG. 13 is a diagram showing a state in which three-pole plug 51 in the present embodiment is
completely inserted into earphone jack 12.
[0077]
As shown in FIG. 13, the voltage setting unit 254 of the present embodiment includes a second
pull-up resistor R4 (= 1 kΩ).
[0078]
The second pull-up resistor R4 is connected between the third node ND4 on the wire between the
terminal B (RCH) of the earphone jack 12 and the second audio output unit 153 and the bias
voltage RBIAS (= 2.0 V). Connected between.
[0079]
When the three-pole plug 51 is completely inserted into the earphone jack 12, the voltages of the
first node ND1 and the fourth node ND3 change in the same manner as the method shown in FIG.
Therefore, in the same manner as in the method shown in FIG. 10, full insertion of the three-pole
plug 51 into the earphone jack 12 and identification that the inserted plug is the three-pole plug
51 are performed.
[0080]
FIG. 14 is a diagram showing a state in which four-pole plug 52 in the present embodiment is
completely inserted into earphone jack 12.
[0081]
When the four-pole plug 52 is completely inserted into the earphone jack 12, the voltages of the
first node ND1 and the fourth node ND3 change in the same manner as the method shown in FIG.
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18
Therefore, in the same manner as the method shown in FIG. 11, the four-pole plug 52 is
completely inserted into the earphone jack 12 and identification is made that the inserted plug is
the four-pole plug 52.
[0082]
FIG. 15 is a diagram showing a state in which 4-pole plug 52 in the present embodiment is
inserted halfway into earphone jack 12.
[0083]
When the four-pole plug 52 is partially inserted into the earphone jack 12, the voltages of the
first node ND1 and the fourth node ND3 are different from the state of the system shown in FIG.
[0084]
In this state, the first node ND1 is connected to the power supply voltage VDD via the first pullup resistor R1 (= 100 kΩ), as in the system shown in FIG. It is connected to the ground 155
through the terminal (L), the terminal A (LCH), and the first pull-down resistor R2 (= 10 kΩ).
Furthermore, in the present embodiment, the first node ND1 is biased via the terminal A ′
(DET), the left audio terminal (L), the terminal B (RCH), and the second pull-up resistor R4 (= 1
kΩ). It is connected to voltage RBIAS (= 2.0 V).
Since the resistance value of the second pull-up resistor R4 is small, the first node ND1 is pulled
up by the bias voltage RBIAS, the voltage of the first node ND1 becomes high level (H), and the
detection signal input to GPIO̲0 DET becomes high (H).
[0085]
Since the detection signal DET is high level (H), it is normally determined that the plug is not
completely inserted in the earphone jack 12.
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As a result, since the type of plug and the determination of the momentary switch are not
performed, the plug inserted in the earphone jack 12 is erroneously determined to be the threepole plug 51 as in the method shown in FIG. Even when the switch 161 is off, an erroneous
determination that the momentary switch 161 is set to on can be prevented.
[0086]
FIG. 16 is a flow chart showing a procedure for determining whether the plug 51 or 52 is
inserted, for identifying the type of the plug 51 or 52, and for identifying the setting of the
momentary switch 161.
[0087]
Referring to FIGS. 13 to 16, in step S102, CPU 2 determines the level of detection signal DET.
[0088]
As shown in FIG. 15, when the four-pole plug 52 is inserted halfway into the earphone jack 12,
the first node ND1 becomes high level (H) as described above.
[0089]
On the other hand, as shown in FIGS. 13 and 14, when the three-pole plug 51 or the four-pole
plug 52 is completely inserted in the earphone jack 12, the first node ND1 is at the low level (L ).
[0090]
If the detection signal DET is at the low level (L), the process proceeds to step S103.
In step S103, the CPU 2 determines that the three-pole plug 51 or the four-pole plug 52 is
completely inserted in the earphone jack 12.
[0091]
In step S104, the CPU 2 determines the level of the signal Mic̲SW.
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As shown in FIG. 13, when the three-pole plug 51 is connected to the earphone jack 12, as
described above, the fourth node ND3 is at low level (L), and the signal Mic̲SW input to GPIO̲1
is It becomes high level (H).
[0092]
On the other hand, as shown in FIG. 14, when the four-pole plug 52 is connected to the earphone
jack 12, as described above, the fourth node ND3 becomes high level (H) and is input to GPIO̲1
The signal Mic̲SW goes low (L).
[0093]
In step S104, when the signal Mic̲SW is at the low level (L), the process proceeds to step S105,
and when the signal Mic̲SW is at the high level (H), the process proceeds to step S106.
[0094]
In step S106, the CPU 2 determines that the three-pole plug 51 has been introduced into the
earphone jack 12.
Thereafter, the process proceeds to step S107.
[0095]
In step S107, when the three-pole plug 51 is completely inserted into the earphone jack 12, the
detection signal DET maintains the low level (L), and the detection in step S107 is repeated.
In step S107, when the three-pole plug 51 is detached from the earphone jack 12 or in the
middle of detachment, the detection signal DET changes to the high level (H), and the process
ends.
[0096]
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In step S <b> 105, the CPU 2 determines that the four-pole plug 52 is inserted into the earphone
jack 12.
Thereafter, the process proceeds to step S108.
[0097]
In step S108, when 4-pole plug 52 is completely inserted in earphone jack 12, detection signal
DET maintains the low level (L), and the process proceeds to step S109.
In step S108, when the four-pole plug 52 is detached from the earphone jack 12 or in the middle
of detachment, the detection signal DET changes to the high level (H), and the process ends.
Even in the state as shown in FIG. 15, in the present embodiment, as described above, the
detection signal DET changes to the high level (H).
[0098]
When the momentary switch 161 is set to ON by the user's operation with the four-pole plug 52
completely inserted in the earphone jack 12, the output terminal 74 of the microphone 28 and
the ground terminal 73 of the microphone 29 Connecting.
As a result, the microphone terminal (M) connected to the terminal D (MIC) is connected to the
ground 155, so the signal Mic̲SW becomes high level (H).
[0099]
In step S109, when the signal Mic̲SW is at high level (H), the process proceeds to step S110, and
when the signal Mic̲SW is at low level (L), the process returns to step S108.
[0100]
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In step S110, the CPU 2 determines that the momentary switch 161 of the four-pole plug
earphone is turned on.
[0101]
In step S111, the CPU 2 executes a process in response to the momentary switch 161 being
turned on.
[0102]
The fourth node ND3 is connected to the ground 155 even when the four-pole plug 52 is
partially inserted in the earphone jack 12 as shown in FIG. Mic̲SW becomes high level (H).
However, as shown in FIG. 15, when the four-pole plug 52 is inserted halfway into the earphone
jack 12, the detection signal DET becomes high level (H) (step S108: NO), and the process
proceeds to step S109. Never go to
Therefore, as shown in FIG. 15, when the four-pole plug 52 is inserted halfway into the earphone
jack 12, it is possible to prevent an erroneous determination that the momentary switch 161 of
the four-pole plug earphone is turned on. .
[0103]
As described above, according to the present embodiment, by providing a pull-up resistor with a
small resistance value at the node on the wire between the terminal B and the second audio
output unit 153, the four-pole plug can be used in the earphone jack. It is possible to prevent the
erroneous determination that the partially inserted state is the completely inserted state.
As a result, it is possible to prevent misidentification that the inserted plug is a three-pole plug,
and to prevent erroneous determination that the switch of the four-pole plug earphone is
pressed.
[0104]
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Note that the voltage setting unit may include a resistor that receives the pull-up bias voltage
MICBIAS. That is, in FIGS. 10 to 15, the third pull-up resistor R3 is connected to the fourth node
ND3 on the wiring between the terminal D (MIC) of the earphone jack 12 and the microphone
audio processing unit 151; And the bias voltage MICBIAS (= 2 V).
[0105]
Reference Signs List 1 portable terminal 2 CPU 3 audio processing unit 11 GPIO interface 13a,
13b, 23a, 23b silicon cap, 16a, 16b, 26a, 26b housing, 17a, 17b, 27a, 27b, 63 speaker, 28, 62
microphone , 51 3-pole plug, 52 4-pole plug, 61 antenna, 64-key input unit, 65 display, 66
memory, 91 3-pole plug earphone, 92 4-pole plug earphone, 94 earphone jack, 71a, 71b, 95a,
95b input terminal , 72a, 72b, 96a, 96b ground terminal 74, output terminal 151 microphone
sound processing unit 152, 153 sound output unit 154, 254 voltage setting unit 155 ground L
left audio terminal R right audio terminal G Ground terminal, M microphone terminal, A, A ', B, C,
Earphone jack of the terminal, IV inverter, R1, R2, R4, RX, RY resistance.
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