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JP2012227950

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This translation is machine-generated. It cannot be guaranteed that it is intelligible, accurate,
complete, reliable or fit for specific purposes. Critical decisions, such as commercially relevant or
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DESCRIPTION JP2012227950
An object of the present invention is to provide a technique for reducing an increase in resistance
of the upper electrode, damage to the membrane, and a decrease in insulation resistance between
the upper electrode and the lower electrode even if a step is generated by dividing the lower
electrode into each element. A plurality of lower electrodes (203), an insulating film (204)
covering the lower electrodes, a plurality of hollow portions (205) formed on the insulating film
(204) so as to overlap the lower electrodes (203) A film 3401, an insulating film 206 covering
the cavity portion 205 and the insulating film 3401, a plurality of upper electrodes 207 formed
on the insulating film 206 so as to overlap with the cavity portion 205, and a plurality of wirings
208 connecting them In the acoustic transducer, the surface of the cavity 205 and the surface of
the insulating film 3401 are flattened to the same height. [Selected figure] Fig. 34
Method of manufacturing ultrasonic transducer
[0001]
The present invention relates to an ultrasonic transducer and a method of manufacturing the
same. In particular, the present invention relates to an ultrasonic transducer manufactured by
MEMS (Micro Electro Mechanical System) technology and its optimum manufacturing method.
[0002]
Ultrasonic transducers are used in diagnostic devices such as tumors in the human body by
transmitting and receiving ultrasonic waves.
04-05-2019
1
[0003]
So far, ultrasonic transducers that use the vibration of a piezoelectric material have been used,
but with the recent advances in MEMS technology, a vibration unit with a structure in which a
cavity is sandwiched between electrodes was fabricated on a silicon substrate Capacitive
micromachined ultrasonic transducers (CMUTs) have been actively developed for practical use.
[0004]
For example, US Pat. No. 6,320,239 B1 (Patent Document 1) discloses a CMUT using a silicon
substrate as a lower electrode.
[0005]
Further, U.S. Pat. No. 6,271,620 B1 (patent document 2) and 2003 IEEE ULTRASONICS
SYMPOSIUM, p577-p580 (non-patent document 1) disclose a CMUT having a structure formed
on a patterned lower electrode.
[0006]
Also, U.S. Pat. No. 6,571,445 B2 (Patent Document 3) and U.S. Pat. No. 6,562,650 B2 (Patent
Document 4) disclose a technique for forming a CMUT on the upper layer of a signal processing
circuit formed on a silicon substrate. ing.
[0007]
U.S. Pat. No. 6,320,239 B1 U.S. Pat. No. 6,271,620 B1 U.S. Pat. No. 6,571,445 B2 U.S. Pat. No.
6,562,650 B2
[0008]
2003 IEEE ULTRASONICS SYMPOSIUM、p577−p580
[0009]
By the way, the CMUT has advantages such as wider usable frequency band of ultrasonic waves
or higher sensitivity as compared with the conventional piezoelectric transducer.
04-05-2019
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In addition, microfabrication is possible because the LSI fabrication technology is used.
In particular, in the case where the elements are arranged in an array, the upper electrode and
the lower electrode of the elements are orthogonally arranged, and the elements at the cross
points are controlled independently, or when the elements are completely independently
controlled. Is considered essential.
The reason is that wiring to each element is required, and the number of wirings in the array can
be enormous, but since it can be manufactured using LSI processing technology, fine wiring is
possible, and further The reason is that the CMUT can also mix the signal processing circuit from
the ultrasonic wave transmitting / receiving unit on one chip.
[0010]
The basic structure and operation of the CMUT array will be described with reference to FIGS.
[0011]
FIG. 1 is a top view of a CMUT array.
The reference numeral 203 denotes a lower electrode, 205 denotes a cavity, 207 denotes an
upper electrode, 208 denotes a wire connecting the upper electrode, and 210 denotes a wet
etching hole for forming the cavity 205.
That is, the wet etching hole 210 is connected to the hollow portion 205.
Reference numeral 101 denotes a pad opening to a pad provided in the same layer as the lower
electrode in order to supply power to the upper electrode 207, and reference numeral 102
denotes a plug for connecting the pad and the wiring 208.
That is, the pad is connected to the wiring 208 connecting the upper electrode 207 through the
plug 102.
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Reference numeral 103 denotes a pad opening for supplying power to the lower electrode 203.
An insulating film is formed between the upper electrode 207 and the wiring 208, and the lower
electrode 203 so as to cover the lower electrode 203 and the cavity 205, but is not shown in
order to show the cavity 205 and the lower electrode 203. .
[0012]
2A shows a cross section in the A-A 'direction of FIG. 1, and FIG. 2B shows a cross section in the
B-B' direction of FIG. As shown in FIGS. 2A and 2B, the lower electrode 203 is formed on the
insulating film 202 formed on the semiconductor substrate 201. A cavity 205 is formed on the
lower electrode 203 via the insulating film 204. An insulating film 206 is formed so as to cover
the hollow portion 205, and a wire 208 connecting the upper electrode 207 and the upper
electrode is formed on the insulating film 206. An insulating film 209 and an insulating film 211
are formed over the upper electrode 207 and the wiring 208. In the insulating film 206 and the
insulating film 209, wet etching holes 210 penetrating these films are formed. The wet etching
holes 210 are formed to form the hollow portion 205, and are filled with the insulating film 211
after the hollow portion 205 is formed.
[0013]
As is apparent from FIGS. 1 and 2, since the upper electrode and the lower electrode are
orthogonal to each other, the wiring connecting the upper electrode has a structure that goes
over the step portion of the lower electrode.
[0014]
The operation of transmitting an ultrasonic wave will be described below.
When a DC voltage and an AC voltage are superimposed on the pad opening 101 connected to
the upper electrode 207 and the pad opening 103 to the lower electrode 203, electrostatic force
acts between the upper electrode 207 and the lower electrode 203, and the upper electrode and
the lower electrode The upper electrode 207 and the insulating films 206, 209 and 211 on the
cavity portion 205 constituting the membrane of the CMUT cell of the cross point where the
electrodes intersect vibrate at the frequency of the alternating voltage applied and transmit
ultrasonic waves.
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[0015]
Conversely, in the case of receiving an ultrasonic wave, the pressure of the ultrasonic wave that
has reached the surface of the device vibrates the insulating films 206, 209, 211 and the upper
electrode 207 on the cavity 205. Since the distance between the upper electrode 207 and the
lower electrode 203 changes due to this vibration, ultrasonic waves can be detected as a change
in electric capacitance between the electrodes. That is, as the distance between the electrodes
changes, the capacitance between the electrodes changes and current flows. By detecting this
current, ultrasonic waves can be detected.
[0016]
As is apparent from the above principle of operation, vibration of the membrane due to
electrostatic force caused by voltage application between the electrodes and change in
capacitance between the electrodes due to vibration cause transmission and reception of
ultrasonic waves. The stability of the voltage difference, the distance between the electrodes and
the thickness of the membrane are important points to ensure stable operation and reliability of
the device.
[0017]
Patent Document 1 discloses a CMUT array using a silicon substrate on which ions are implanted
as a lower electrode.
However, in this structure, since the resistance of the silicon substrate is large, in order to
suppress the voltage drop of the lower electrode inside the CMUT array, the drive power supply
from the outside needs to be performed close to the CMUT. When many CMUTs are arranged,
many power supply points are also required.
[0018]
Patent documents 2, 3, 4 and Non-patent document 1 disclose a structure using a metal film for
the lower electrode of a CMUT array. Patent Documents 2, 3 and 4 disclose examples of a lower
04-05-2019
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electrode with a thickness of 250 nm to 500 nm using materials such as aluminum (Al), tungsten
(W), and copper (Cu), and Non-Patent Document 1 discloses a material of chromium. An example
of a 150 nm thick bottom electrode is shown. However, even in the case of the lower electrode
using the metal film described above, the lower electrode having a thickness of 500 nm or more
is essential in order to suppress the voltage drop inside the CMUT array.
[0019]
Therefore, the step of the lower electrode of 500 nm or more inevitably occurs by dividing the
lower electrode into each element. The wiring connecting the upper electrode gets over this step,
but when forming the metal film to be the wiring, the coverage of the metal film at the step falls
below that of the flat part, and the film thickness of the metal film at the step Becomes thinner.
As a result, it causes an increase in the resistance of the upper electrode. In addition, when
processing the upper electrode pattern, it is necessary to perform excessive etching to remove
the extra metal film at the stepped portion, and damage such as scraping of the base film of the
metal film occurs. This means that the membrane constituting the membrane of the CMUT cell
becomes thinner, which causes the frequency characteristic fluctuation of the CMUT cell.
Furthermore, since the coverage of the insulating film which insulates the lower electrode and
the upper electrode is also lower at the step portion than at the flat portion, the insulation
resistance is also lowered by thinning the thickness of the insulating film at the step portion. Sex
is reduced.
[0020]
Further, the step formed by the hollow portion also has a structure in which the wiring
connecting the upper electrode passes over, which leads to a decrease in device stability and
reliability as in the step formed by the lower electrode. In particular, when the membrane is
greatly vibrated to generate strong transmission sound, it is necessary to secure a large movable
range of the membrane, and therefore, it is necessary to increase the thickness of the hollow
portion. The impact can not be ignored.
[0021]
Therefore, it is an object of the present invention to increase the resistance of the upper
electrode, damage to the membrane, and the insulation resistance between the upper electrode
and the lower electrode even if the lower electrode is divided into each element or the step due
to the cavity is generated. It is an object of the present invention to provide a structure and a
04-05-2019
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manufacturing method that suppress the reduction.
[0022]
The above and other objects and novel features of the present invention will be apparent from
the description of the present specification and the accompanying drawings.
[0023]
The outline of typical ones of the inventions disclosed in the present application will be briefly
described as follows.
[0024]
The ultrasonic transducer according to the present invention is arranged such that (a) a first
electrode, (b) a first insulating film covering the first electrode, and (c) the first insulating film so
as to overlap the first electrode. (D) a second insulating film covering the cavity, (e) a second
electrode disposed on the second insulating film so as to overlap with the cavity, (f) the second
electrode And a wire connected to the two electrodes, wherein the width of the wire overlapping
when viewed from the top surface of the first electrode is greater than the width of the wire not
overlapping when viewed from the top surface of the first electrode. It is characterized by
[0025]
Further, in the ultrasonic transducer according to the present invention, (a) a first electrode, (b) a
first insulating film covering the first electrode, and (c) overlapping the first electrode on the first
insulating film. (D) a second insulating film covering the cavity, (e) a second electrode disposed
on the second insulating film so as to overlap with the cavity, (f) A wiring connected to the
second electrode is provided, and the outer peripheral portion of the first electrode has a taper
angle, whereby the step of the first electrode is alleviated.
And, the step by the first electrode is 500 nm or more.
Furthermore, when viewed from above, the width of the wire overlapping the outer periphery of
the first electrode is thicker than the width of the wire not overlapping the outer periphery of the
first electrode when viewed from above It is.
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[0026]
Further, in the ultrasonic transducer according to the present invention, (a) a first electrode, (b) a
first insulating film covering the first electrode, and (c) overlapping the first electrode on the first
insulating film. (D) a second insulating film covering the cavity, (e) a second electrode disposed
on the second insulating film so as to overlap with the cavity, (f) A wiring connected to the
second electrode is provided, and a side wall made of an insulating film is formed on an outer
peripheral portion of the first electrode, whereby a level difference of the first electrode is
alleviated.
And, the step by the first electrode is 500 nm or more.
Furthermore, when viewed from above, the width of the wire overlapping with the sidewall is
larger than the width of the wire not overlapping with the sidewall when viewed from above.
[0027]
Further, in the ultrasonic transducer according to the present invention, (a) a first electrode, (b) a
first insulating film covering the first electrode, and (c) overlapping the first electrode on the first
insulating film. (D) a second insulating film covering the cavity, (e) a second electrode disposed
on the second insulating film so as to overlap with the cavity, (f) A wiring connected to the
second electrode may be provided, and one or both of the step by the first electrode and the step
by the hollow portion may be alleviated.
[0028]
In the ultrasonic transducer according to the present invention, (a) a first electrode, (b) a first
insulating film filling the space between the first electrodes, and (c) covering the first electrode
and the first insulating film A second insulating film, (d) a hollow portion disposed on the second
insulating film so as to overlap the first electrode, (e) a third insulating film covering the hollow
portion, (f) the third insulating film 3) A second electrode disposed on the insulating film so as to
overlap with the cavity, and (g) a wire connected to the second electrode, wherein the first
electrode and the surface of the first insulating film have the same height Is characterized in that
it is flat.
04-05-2019
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And, the thickness of the first electrode is 500 nm or more.
[0029]
Further, in the ultrasonic transducer according to the present invention, (a) a first electrode, (b) a
first insulating film covering the first electrode, and (c) overlapping the first electrode on the first
insulating film. (D) a second insulating film filling the space between the hollows, (e) a third
insulating film covering the hollows and the second insulating film, (f) the third insulating film A
second electrode disposed on the insulating film so as to overlap with the cavity, and (g) a wire
connected to the second electrode, wherein the surface of the cavity and the surface of the
second insulating film are at the same height It is characterized in that it is flattened.
[0030]
The method of manufacturing an ultrasonic transducer according to the present invention
comprises the steps of: (a) patterning a conductive film to form a first electrode; (b) forming a
first insulating film covering the first electrode; ) Planarizing the first insulating film to expose
the surface of the first electrode; (d) forming a second insulating film covering the first electrode
and the first insulating film; Forming a sacrificial layer on the second insulating film so as to
overlap the first electrode; (f) forming a third insulating film covering the sacrificial layer and the
second insulating film; (g) Forming a second electrode overlapping the sacrificial layer on the
third insulating film, (h) forming a wire connected to the second electrode, (i) forming the second
electrode, the wire, and the wire Forming a fourth insulating film covering the third insulating
film; (j) the third insulating film and Forming an opening through the fourth insulating film to
reach the sacrificial layer; (k) forming a cavity by removing the sacrificial layer using the
opening; And a step of filling the opening with a fifth insulating film and sealing the cavity.
And, the thickness of the first electrode is 500 nm or more.
[0031]
Further, the method of manufacturing an ultrasonic transducer according to the present
invention comprises the steps of: (a) patterning a conductive film to form a first electrode; and (b)
forming a first insulating film covering the first electrode. (C) forming a sacrificial layer on the
first insulating film so as to overlap with the first electrode; (d) forming a second insulating film
covering the sacrificial layer and the first insulating film; (E) planarizing the second insulating
film to expose the surface of the sacrificial layer; (f) forming a third insulating film covering the
04-05-2019
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second insulating film and the sacrificial layer; (g) Forming a second electrode overlapping the
sacrificial layer on the third insulating film, (h) forming a wire connected to the second electrode,
(i) forming the second electrode, the wire, and the wire Forming a fourth insulating film covering
the third insulating film; (j) forming the third insulating film; Forming an opening through the
fourth insulating film to reach the sacrificial layer; (k) forming a cavity by removing the sacrificial
layer using the opening; And a step of filling the opening with a fifth insulating film and sealing
the cavity.
[0032]
Further, the method of manufacturing an ultrasonic transducer according to the present
invention comprises the steps of: (a) patterning a conductive film to form a first electrode; and (b)
forming a first insulating film covering the first electrode. (C) forming a sacrificial layer on the
first insulating film so as to overlap the first electrode, (d) forming a second insulating film
covering the sacrificial layer, and (e) the second Forming a second electrode overlapping the
sacrificial layer on the insulating film, (f) forming a wire connected to the second electrode, and
(g) forming the second electrode, the wire, and the second insulation. Forming a third insulating
film covering the film; (h) forming an opening penetrating the second insulating film and the
third insulating film to reach the sacrificial layer; (i) the opening Forming a cavity by removing
the sacrificial layer using (4) filling the opening with an insulating film and sealing the hollow
portion, and in the step of forming the wiring, the width of the wiring overlapping the outer
peripheral portion of the first electrode as viewed from above is In view of the above, it is
characterized in that it is formed thicker than the width of the wiring which does not overlap
with the outer peripheral portion of the first electrode.
[0033]
Further, the method of manufacturing an ultrasonic transducer according to the present
invention comprises the steps of: (a) patterning a conductive film to form a first electrode; and (b)
forming a first insulating film covering the first electrode. (C) forming a sacrificial layer on the
first insulating film so as to overlap the first electrode, (d) forming a second insulating film
covering the sacrificial layer, and (e) the second Forming a plurality of second electrodes
overlapping the sacrificial layer on the insulating film, (f) forming a wire connected to the second
electrode, (g) forming the second electrode, the wire, and the second (2) forming a third
insulating film covering the insulating film, (h) forming an opening penetrating the second
insulating film and the third insulating film to reach the sacrificial layer, (i) the above Forming a
cavity by removing the sacrificial layer using an opening; ) Filling the opening with a fourth
insulating film and sealing the cavity, and forming the first electrode so that the outer periphery
of the first electrode has a taper angle in the step of forming the first electrode. It is
04-05-2019
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characterized by
And, the thickness of the first electrode is 500 nm or more.
Furthermore, in the step of forming the wiring, the width of the wiring overlapping with the
outer peripheral portion of the first electrode as viewed from the top surface is greater than the
width of the wiring not overlapping with the outer peripheral portion of the first electrode as
viewed from the top surface It is also characterized in that it is formed thick.
[0034]
Further, the method of manufacturing an ultrasonic transducer according to the present
invention comprises the steps of: (a) patterning a conductive film to form a first electrode; and (b)
forming a first insulating film covering the first electrode. (C) etching the first insulating film to
form sidewalls on the outer peripheral portion of the first electrode; and (d) forming a second
insulating film covering the first electrode and the sidewalls. (E) forming a sacrificial layer
overlapping the first electrode on the second insulating film, (f) forming a third insulating film
covering the sacrificial layer and the second insulating film, g) forming a plurality of second
electrodes overlapping the sacrificial layer on the third insulating film, (h) forming a wiring
connected to the second electrode, and (i) forming the second electrode A process for forming a
fourth insulating film covering the wiring and the third insulating film And (j) forming an opening
penetrating the third insulating film and the fourth insulating film to reach the sacrificial layer,
and (k) removing the sacrificial layer using the opening. And forming a hollow portion by the
fifth insulating film, and sealing the hollow portion. And, the thickness of the first electrode is
500 nm or more. Furthermore, in the step of forming the wiring, the width of the wiring
overlapping with the sidewall as viewed from above is formed to be wider than the width of the
wiring not overlapping with the sidewall as viewed from above. It is.
[0035]
Further, the method of manufacturing an ultrasonic transducer according to the present
invention comprises the steps of: (a) patterning a first insulating film to form a first recess; and
(b) embedding a first conductive film in the first recess. (C) planarizing the first conductive film
until the surface of the first insulating film is exposed, and forming a first electrode embedded in
the first insulating film; (d) the first electrode and Forming a second insulating film covering the
04-05-2019
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first insulating film; (e) forming a sacrificial layer on the second insulating film so as to overlap
the first electrode; (f) the sacrificial layer and Forming a third insulating film covering the second
insulating film, (g) forming a second electrode overlapping the sacrificial layer on the third
insulating film, and (h) connecting to the second electrode Forming an interconnect, (i) the
second electrode, the interconnect, and the third insulating film Forming a covering fourth
insulating film; (j) forming an opening penetrating the third insulating film and the fourth
insulating film to reach the sacrificial layer; (k) using the opening Forming a cavity by removing
the sacrificial layer, and (l) filling the opening with a fifth insulating film to seal the cavity. . The
depth of the first depression is 500 nm or more.
[0036]
Further, the method of manufacturing an ultrasonic transducer according to the present
invention comprises the steps of: (a) patterning a conductive film to form a first electrode; and (b)
forming a first insulating film covering the first electrode. (C) forming a second insulating film
covering the first insulating film, (d) forming a plurality of first recesses reaching the first
insulating film in the second insulating film, and (e) A step of embedding a film to be a sacrificial
layer in the first recess, and (f) planarizing the film to be a sacrificial layer until the surface of the
second insulating film is exposed, and the sacrificial layer embedded in the second insulating film
Forming a third insulating film covering the sacrificial layer and the second insulating film, and
(h) forming a second electrode overlapping the sacrificial layer on the third insulating film. (I)
forming a wire connected to the second electrode; (j) Forming a fourth insulating film covering
the electrode, the wiring, and the third insulating film; (k) forming an opening penetrating the
third insulating film and the fourth insulating film to reach the sacrificial layer And (l) forming a
cavity by removing the sacrificial layer using the opening, and (m) filling the opening with a fifth
insulating film and sealing the cavity. And is characterized in that
[0037]
The effects obtained by typical ones of the inventions disclosed in the present application will be
briefly described as follows.
[0038]
By reducing the difference in level between the lower electrode and the cavity, the reduction in
film thickness of the upper electrode at the difference in level between the lower electrode and
the cavity can be reduced, so that the increase in resistance can be suppressed.
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In addition, damage to the membrane in upper electrode processing can also be reduced.
Furthermore, the structure which can also suppress the fall of the insulation tolerance between
an upper electrode and a lower electrode, and its manufacturing method can be provided.
[0039]
It is a top view of the ultrasonic transducer which the present inventors examined. (A) is sectional
drawing cut ¦ disconnected by the A-A 'line ¦ wire of FIG. 1, FIG. 3, (b) is sectional drawing cut ¦
disconnected by the B-B' line ¦ wire of FIG. 1, FIG. It is the top view which showed the ultrasonic
transducer in Embodiment 1 of this invention. (A) is a sectional view showing the manufacturing
process of the ultrasonic transducer in the section cut by the AA 'line of FIG. 3, (b) is a section by
the BB' line of FIG. It is sectional drawing which showed the manufacturing process of an
ultrasonic transducer. (A) is sectional drawing which showed the manufacturing process of the
ultrasonic transducer following FIG. 4 (a), (b) is sectional drawing which showed the
manufacturing process of the ultrasonic transducer following FIG. 4 (b). (A) is sectional drawing
which showed the manufacturing process of the ultrasonic transducer following FIG. 5 (a), (b) is
sectional drawing which showed the manufacturing process of the ultrasonic transducer
following FIG. 5 (b). (A) is sectional drawing which showed the manufacturing process of the
ultrasonic transducer following FIG. 6 (a), (b) is sectional drawing which showed the
manufacturing process of the ultrasonic transducer following FIG. 6 (b). (A) is sectional drawing
which showed the manufacturing process of the ultrasonic transducer following FIG. 7 (a), (b) is
sectional drawing which showed the manufacturing process of the ultrasonic transducer
following FIG. 7 (b). (A) is sectional drawing which showed the manufacturing process of the
ultrasonic transducer following FIG. 8 (a), (b) is sectional drawing which showed the
manufacturing process of the ultrasonic transducer following FIG. 8 (b). (A) is sectional drawing
which showed the manufacturing process of the ultrasonic transducer following FIG. 9 (a), (b) is
sectional drawing which showed the manufacturing process of the ultrasonic transducer
following FIG.9 (b). (A) is sectional drawing which showed the manufacturing process of the
ultrasonic transducer following FIG. 10 (a), (b) is sectional drawing which showed the
manufacturing process of the ultrasonic transducer following FIG. 10 (b). It is the top view which
showed the ultrasonic transducer in Embodiment 1 of this invention. It is the top view which
showed the ultrasonic transducer in Embodiment 1 of this invention. It is the top view which
showed the ultrasonic transducer in Embodiment 2 of this invention. (A) is sectional drawing cut
¦ disconnected by the A-A 'line ¦ wire of FIG. 14, (b) is sectional drawing cut ¦ disconnected by the
B-B' line ¦ wire of FIG. It is the top view which showed the ultrasonic transducer in Embodiment 3
of this invention. (A) is sectional drawing cut ¦ disconnected by the A-A 'line ¦ wire of FIG. 16, (b)
is sectional drawing cut ¦ disconnected by the B-B' line ¦ wire of FIG.
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(A) is a sectional view showing the manufacturing process of the ultrasonic transducer in the
section cut along the line AA 'in FIG. 16, (b) is a section in the section cut along the line BB' in
FIG. It is sectional drawing which showed the manufacturing process of an ultrasonic transducer.
(A) is sectional drawing which showed the manufacturing process of the ultrasonic transducer
following FIG. 18 (a), (b) is sectional drawing which showed the manufacturing process of the
ultrasonic transducer following FIG. 18 (b). FIG. 19 (a) is a cross sectional view showing the
manufacturing process of the ultrasonic transducer continued from FIG. 19 (a), and FIG. 19 (b) is
the cross sectional view showing the manufacturing process of the ultrasonic transducer
following FIG. It is the top view which showed the ultrasonic transducer in Embodiment 4 of this
invention. FIG. 21A is a cross-sectional view taken along line A-A ′ of FIG. 21, and FIG. 21B is a
cross-sectional view taken along line B-B ′ of FIG. 21. (A) is a sectional view showing the
manufacturing process of the ultrasonic transducer in the section cut along the line AA 'in FIG.
21, (b) is a section in the section cut along the line BB' in FIG. It is sectional drawing which
showed the manufacturing process of an ultrasonic transducer. FIG. 23 (a) is a cross-sectional
view showing the manufacturing process of the ultrasonic transducer following FIG. 23 (a), and
FIG. 23 (b) is the cross-sectional view showing the manufacturing process of the ultrasonic
transducer following FIG. (A) is a sectional view showing the manufacturing process of the
ultrasonic transducer in the section cut along the line AA 'in FIG. 21, (b) is a section in the section
cut along the line BB' in FIG. It is sectional drawing which showed the manufacturing process of
an ultrasonic transducer. (A) is sectional drawing which showed the manufacturing process of the
ultrasonic transducer following FIG. 25 (a), (b) is sectional drawing which showed the
manufacturing process of the ultrasonic transducer following FIG. 25 (b). FIG. 26 (a) is a crosssectional view showing the manufacturing process of the ultrasonic transducer following FIG. 26
(a), and FIG. 26 (b) is the cross-sectional view showing the manufacturing process of the
ultrasonic transducer following FIG. (A) is a cross-sectional view showing the manufacturing
process of the ultrasonic transducer following FIG. 27 (a), and (b) is a cross-sectional view
showing the manufacturing process of the ultrasonic transducer following FIG. It is the top view
which showed the ultrasonic transducer in Embodiment 5 of this invention. (A) is a crosssectional view cut along a line A-A 'in FIG. 29, (b) is a cross-sectional view cut along a line B-B' in
FIG. (A) is a cross sectional view showing the manufacturing process of the ultrasonic transducer
in the cross section cut along the line AA 'in FIG. 29, (b) is a cross sectional view cut in the line
BB' in FIG. It is sectional drawing which showed the manufacturing process of an ultrasonic
transducer.
(A) is a cross-sectional view showing the manufacturing process of the ultrasonic transducer
following FIG. 31 (a), and (b) is a cross-sectional view showing the manufacturing process of the
ultrasonic transducer following FIG. 31 (b). (A) is a sectional view showing a manufacturing
process of an ultrasonic transducer following FIG. 32 (a), (b) is a sectional view showing a
04-05-2019
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manufacturing process of an ultrasonic transducer following FIG. 32 (b). It is sectional drawing of
the ultrasonic transducer in Embodiment 6 of this invention. (A) is sectional drawing cut ¦
disconnected by the A-A 'line ¦ wire of FIG. 1, (b) is sectional drawing cut ¦ disconnected by the BB' line ¦ wire of FIG. (A) is a cross sectional view showing the manufacturing process of the
ultrasonic transducer shown in FIG. 34 (a), (b) is a cross sectional view showing the
manufacturing process of the ultrasonic transducer shown in FIG. 34 (b) is there. (A) is sectional
drawing which showed the manufacturing process of the ultrasonic transducer following (a) of
FIG. 35, (b) is sectional drawing which showed the manufacturing process of the ultrasonic
transducer following (b) of FIG. FIG. 36 (a) is a cross-sectional view showing the manufacturing
process of the ultrasonic transducer following FIG. 36 (a), and FIG. 36 (b) is the cross-sectional
view showing the manufacturing process of the ultrasonic transducer following FIG. It is the top
view which showed the ultrasonic transducer in Embodiment 7 of this invention. FIG. 38A is a
cross-sectional view taken along line A-A ′ of FIG. 38, and FIG. 38B is a cross-sectional view
taken along line B-B ′ of FIG. 38. It is the top view which showed the ultrasonic transducer in
Embodiment 8 of this invention. FIG. 40 (a) is a cross-sectional view taken along the line A-A 'in
FIG. 40; FIG. 40 (b) is a cross-sectional view taken along the line B-B' in FIG. It is the top view
which showed the ultrasonic transducer in Embodiment 9 of this invention. FIG. 42 (a) is a crosssectional view taken along line A-A 'in FIG. 42; FIG. 42 (b) is a cross-sectional view taken along
line B-B' in FIG.
[0040]
In the following embodiments, when it is necessary for the sake of convenience, it will be
described by dividing into a plurality of sections or embodiments, but they are not unrelated to
each other unless specifically stated otherwise, one is the other And some or all of the variations,
details, and supplementary explanations.
[0041]
Further, in the following embodiments, when referring to the number of elements (including the
number, numerical value, quantity, range, etc.), it is particularly pronounced and clearly limited
to a specific number in principle. It is not limited to the specific number except for the number,
and may be more or less than the specific number.
[0042]
Furthermore, in the following embodiments, the constituent elements (including element steps
and the like) are not necessarily essential unless explicitly stated or considered to be obviously
essential in principle. Needless to say.
04-05-2019
15
[0043]
Similarly, in the following embodiments, when referring to the shape, positional relationship, etc.
of components etc., unless specifically stated otherwise and in principle not considered otherwise
in principle, etc., It includes those that are similar or similar to the shape etc.
The same applies to the above numerical values and ranges.
[0044]
Hatching may be added to facilitate understanding even if it is a plan view.
[0045]
In the description of the embodiment below, the ultrasonic transducer has the purpose of
suppressing the increase in resistance of the upper electrode, reducing the damage to the
membrane, and suppressing the decrease in insulation resistance between the upper and lower
electrodes. This is realized by making the wiring width connecting the lines thicker and making
the step portion be a relaxed structure.
[0046]
First Embodiment FIG. 3 is a top view of a CMUT array according to a first embodiment.
403 is a lower electrode, 412 is a cavity, 407 is an upper electrode, 408 is a wire connecting the
upper electrode, and 411 is a wet etching hole for forming a cavity.
That is, the wet etching hole 411 is connected to the hollow portion 412.
Reference numeral 301 denotes a pad opening to a pad provided in the same layer as the lower
electrode for supplying power to the upper electrode 407, and reference numeral 302 denotes a
plug for connecting the pad and the wiring 408.
04-05-2019
16
That is, the pad is connected to the wiring 408 connecting the upper electrode 407 through the
plug 302. Reference numeral 303 denotes a pad opening for supplying power to the lower
electrode 403. An insulating film is formed between the upper electrode 407 and the wiring 408,
and the lower electrode 403 so as to cover the lower electrode 403 and the cavity 412, but the
insulating film is not shown in order to show the cavity 412 and the lower electrode 403. . The AA 'cross section and the B-B' cross section of FIG. 3 are the same as those of FIG.
[0047]
The feature of the first embodiment is that, as indicated by 409 in FIG. 3, the wiring width of the
wiring 408 connecting the upper electrode at the stepped portion of the lower electrode 403 is
wider than the wiring width other than the stepped portion. . With such a configuration, an
increase in the resistance of the wiring can be suppressed even if the coverage is lower than that
of the flat portion and the film thickness becomes thinner at the step portion when the
conductive film to be the upper electrode 407 and the wiring 408 is deposited. . That is, even if
the film thickness of the wiring 409 is reduced in the stepped portion, the increase in the
resistance of the wiring 409 in the stepped portion can be suppressed by thickening the wiring
width of the wiring 409. The wiring width of the wiring 409 is, for example, about twice as large
as the wiring width of the wiring 408. Specifically, for example, if the wiring width of the wiring
408 is about 3 μm, the wiring width of the wiring 409 is about 6 μm.
[0048]
In addition, by increasing the wiring width of only the step portion, the overlapping portion
between the lower electrode 403 and the wiring 408 connecting the upper electrode is not
significantly increased, and an increase in parasitic capacitance between the lower electrode 403
and the wiring 408 is also suppressed. be able to. In FIG. 3, although the widening of the wiring
is performed at all between the stepped portions of the opposed lower electrodes 403, it is
obvious that only the stepped portion may be widened. In particular, when the thickness of the
lower electrode 403 is 500 nm or more in order to lower the resistance of the lower electrode
403, the step due to the lower electrode 403 becomes 500 nm or more. Then, in the step portion
at the time of depositing the conductive film to be the upper electrode 407 and the wiring 408,
the fact that the coverage is lower than the flat portion and the film thickness becomes thinner
becomes apparent. Therefore, as shown in the first embodiment, the configuration in which the
wiring width of the wiring 409 formed in the step portion of the lower electrode 403 is wider
than the wiring width of the wiring 408 formed in the area other than the step portion is the
lower electrode. This is particularly effective when the step by 403 is 500 nm or more.
04-05-2019
17
[0049]
Next, a method of manufacturing the CMUT array described in the first embodiment will be
described using the drawings. (A) in FIGS. 4 to 11 shows a cross section in the direction of AA 'in
FIG. 3, and (b) in FIGS. 4 to 11 is in the direction of BB' in FIG. The cross section is shown.
[0050]
First, as shown in FIGS. 4A and 4B, an insulating film 402 made of a silicon oxide film is
deposited on a semiconductor substrate 401 by plasma CVD (Chemical Vapor Deposition)
method, and then a titanium nitride film is formed by sputtering method. An aluminum alloy film
and a titanium nitride film are stacked to 100 nm, 600 nm, and 100 nm, respectively. Here, an
integrated circuit which performs signal processing and the like can be formed between the
semiconductor substrate 401 and the insulating film 402. For example, a MISFET (Metal
Insulator Semiconductor Field Effect Transistor) is formed on a semiconductor substrate 401,
and a multilayer wiring is formed on the MISFET. Then, the insulating film 402 is formed over
the multilayer wiring. These integrated circuits are formed using conventional semiconductor
fabrication techniques.
[0051]
Thereafter, the lower electrode 403 is formed by patterning by photolithography and dry
etching. An insulating film 404 of silicon oxide film is deposited to 100 nm on the lower
electrode 403 by plasma CVD.
[0052]
Next, a polycrystalline silicon film is deposited to 200 nm on the upper surface of the insulating
film 404 by plasma CVD. Then, the polycrystalline silicon film is left on the lower electrode 403
by photolithography and dry etching. The remaining portion becomes the sacrificial layer 405
and becomes a hollow portion in the subsequent process. (FIG. 5 (a), (b)).
04-05-2019
18
[0053]
Subsequently, an insulating film 406 of silicon oxide is deposited to 200 nm by plasma CVD so as
to cover the sacrificial layer 405 and the insulating film 404. (FIG. 6 (a), (b)).
[0054]
Next, in order to form the upper electrode 407 and the wiring 408 connecting the upper
electrode of the CMUT, 50 nm, 300 nm, and 50 nm of stacked films of a titanium nitride film, an
aluminum alloy film, and a titanium nitride film are deposited by sputtering. Then, the upper
electrode 407 and the wiring 408 are formed by the photolithography technique and the dry
etching technique (FIGS. 7A and 7B). At this time, the wiring 409 in the step portion of the lower
electrode 403 is a mask for photolithography, and the wiring width can be increased only in the
step portion without an additional process by increasing the wiring width.
[0055]
Next, 500 nm of an insulating film 410 of silicon nitride film is deposited by plasma CVD so as to
cover the insulating film 406, the upper electrode 407, and the wiring 408 (FIGS. 8A and 8B).
Subsequently, wet etching holes 411 reaching the sacrificial layer 405 are formed in the
insulating films 410 and 406 using photolithography technology and dry etching technology
(FIGS. 9A and 9B).
[0056]
Thereafter, the sacrificial layer 405 is wet-etched with potassium hydroxide through the wet
etching holes 411 to form a cavity 412 (FIGS. 10A and 10B).
[0057]
Next, in order to bury the wet etching holes 411, an insulating film 413 of silicon nitride film is
deposited to 800 nm by plasma CVD.
04-05-2019
19
(FIG. 11 (a), (b)). Thus, the CMUT array according to the first embodiment can be formed.
[0058]
As described above, according to the CMUT array of the first embodiment, the step coverage at
the step portion when depositing the conductive film to be the upper electrode 407 and the
wiring 408 is lower than that at the flat portion, and the film thickness becomes thinner.
However, by making the wiring width of the wiring 408 connecting the upper electrode at the
stepped portion of the lower electrode 403 wider than the wiring width of the portions other
than the stepped portion, the increase in resistance of the wiring can be suppressed. In addition,
by making the wiring width of only the stepped portion wide, the overlapping portion between
the lower electrode 403 and the wiring 408 connecting the upper electrode does not increase
significantly, and the increase of parasitic capacitance between the lower electrode and the
wiring is also suppressed. it can.
[0059]
The CMUT array shown in FIG. 3 has a configuration in which CMUT cells of two rows and one
column are arranged at the cross point of the lower electrode 403 and the upper electrode 407,
but the same is true even when CMUT cells of many rows and many columns are arranged. . FIG.
12 shows a top view of a mode in which 3 rows and 4 columns of CMUT cells are arranged at
cross points. Also in this case, the same effect can be obtained by increasing the width of the
wiring 409 connecting the upper electrode 407 at the step portion of the lower electrode 403.
Further, in FIG. 12, each of the wires 409 in the step portion of the lower electrode 403 is
thickened, but if the wires connect the same upper electrode, only the step portion of the lower
electrode 403 is collectively as shown in FIG. By the connection, although the parasitic
capacitance of the lower electrode 403 and the wiring 409 is increased, the same effect as the
effect of thickening each wiring can be obtained.
[0060]
In addition, in FIG.3, FIG.12, FIG.13, although CMUT cell is carrying out the shape of a hexagon, a
shape is not restricted to this, For example, you may have circular shape.
[0061]
04-05-2019
20
Moreover, the material which comprises the CMUT cell shown as this Embodiment 1 shows one
of the combination.
The material of the sacrificial layer also needs to ensure the wet etching selectivity with the
material surrounding the sacrificial layer. Therefore, in addition to the polycrystalline silicon film,
an SOG film (spin-on-glass) or a metal film may be used.
[0062]
Second Embodiment The CMUT array according to the second embodiment is characterized in
that the outer peripheral portion of the lower electrode has a tapered shape in order to reduce
the level difference due to the lower electrode.
[0063]
FIG. 14 is a top view of the CMUT array of the second embodiment.
1503 is a lower electrode, 1505 is a cavity, 1507 is an upper electrode, 1508 is a wire
connecting the upper electrode 1507, and 1510 is a wet etching hole for forming the cavity
1505. That is, the wet etching hole 1510 is connected to the hollow portion 1505. Reference
numeral 1401 denotes a pad opening to a pad provided in the same layer as the lower electrode
1503 to supply power to the upper electrode 1507, and reference numeral 1402 denotes a plug
connecting the pad and the wiring 1508. That is, the pad is connected to the wiring 1508
connecting the upper electrode 1507 through the plug 1402. Reference numeral 1403 denotes a
pad opening for supplying power to the lower electrode 1503. A tapered portion 1512 is formed
on the outer peripheral portion of the lower electrode 1503. An insulating film is formed
between the upper electrode 1507 and the wiring 1508 and the lower electrode 1503 so as to
cover the hollow portion 1505, the tapered portion 1512 and the lower electrode 1503, but the
hollow portion 1505, the lower electrode 1503 and the tapered portion 1512 Not shown to
show.
[0064]
04-05-2019
21
15A shows a cross section in the A-A 'direction of FIG. 14, and FIG. 15B shows a cross section in
the B-B' direction of FIG. As shown in FIGS. 15A and 15B, the lower electrode 1503 is formed on
the insulating film 1502 formed on the semiconductor substrate 1501. The side wall of the lower
electrode 1503 is tapered. A cavity 1505 is formed on the lower electrode 1503 via an insulating
film 1504.
[0065]
An insulating film 1506 is formed so as to surround the hollow portion 1505, and a wire 1508
connecting the upper electrode 1507 and the upper electrode is formed on the insulating film
1506.
[0066]
An insulating film 1509 and an insulating film 1511 are formed over the upper electrode 1507
and the wiring 1508.
In the insulating film 1506 and the insulating film 1509, wet etching holes 1510 penetrating
these films are formed. The wet etching hole 1510 is formed to form a cavity 1505 and is filled
with an insulating film 1511 after the cavity 1505 is formed.
[0067]
The feature of the second embodiment is that the outer peripheral portion of the lower electrode
1503 is tapered as shown in FIG. 14 and FIGS. 15 (a) and 15 (b).
[0068]
With such a configuration, the level difference due to the lower electrode 1503 is alleviated, the
step coverage at the level difference portion of the wiring 1508 is improved, and resistance
increase and disconnection of the wiring can be suppressed.
In particular, if the step by the lower electrode 1503 is 500 nm or more, the step coverage at the
step is further reduced. Therefore, when the step by the lower electrode 1503 is 500 nm or
more, it is effective to provide the tapered portion 1512 in the step .
04-05-2019
22
[0069]
Further, when the upper electrode 1507 and the wiring 1508 are patterned, the local level
difference due to the lower electrode 1503 is alleviated, so the amount of over-etching for
removing the wiring material in the level difference portion can be reduced. That is, when the
amount of over-etching is large, the insulating film 1506 in the lower layer of the upper
electrode 1507 is scraped to change the thickness of the membrane of the CMUT cell, which
causes the variation of the operating characteristics. However, in the structure shown in the
second embodiment, by forming the side wall of the lower electrode in a tapered shape, the local
step difference can be alleviated, so the amount of over-etching can be reduced. The amount of
scraping can be reduced and the operation stability can be improved.
[0070]
Furthermore, the insulating films 1504 and 1506 that insulate the lower electrode 1503 and the
upper electrode 1507 are also reduced in film thickness reduction at the stepped portion of the
lower electrode by tapering the side wall of the lower electrode, suppressing the decrease in
insulation resistance. Improve device reliability.
[0071]
Further, as described in the first embodiment, if the wiring width of the wiring overlapping the
tapered portion 1512 of the side wall of the lower electrode 1503 is increased, the resistance
increase and the disconnection of the wiring can be further suppressed.
[0072]
The method of manufacturing the CMUT array according to the second embodiment is
substantially the same as that of the first embodiment except that the side walls are tapered
when the lower electrode 1503 is patterned.
[0073]
In order to make the side wall of the lower electrode 1503 have a taper angle, when patterning
the lower electrode 1503 by the dry etching technique, mixing a deposition gas such as
hydrocarbon with the etching gas of the metal material to be the lower electrode 1503 Can do it.
04-05-2019
23
For example, in the case where the lower electrode 1503 is a laminated film of a titanium nitride
film, an aluminum alloy film, and a titanium nitride film as shown in the first embodiment, an
etching gas containing chlorine is usually used for patterning. By mixing a gas such as
difluoromethane or the like, it can be patterned in a tapered shape with good control.
The tapered shape can also be obtained by patterning the lower electrode 1503 by wet etching.
[0074]
Although the CMUT array shown in FIG. 14 has a configuration in which CMUT cells in two rows
and one column are arranged at the cross point of the lower electrode 1503 and the upper
electrode 1507, as shown in the first embodiment, many rows are provided. Even in the case
where a large number of rows of CMUT cells are arranged, similar effects can be obtained by
patterning the lower electrode in a tapered shape.
[0075]
Further, in FIG. 14, the CMUT cell has a hexagonal shape, but the shape is not limited to this, and
may have, for example, a circular shape.
[0076]
Moreover, the material which comprises the CMUT cell shown as this Embodiment 2 shows one
of the combination.
The material of the sacrificial layer also needs to ensure the wet etching selectivity with the
material surrounding the sacrificial layer.
Therefore, in addition to the polycrystalline silicon film, an SOG film or a metal film may be used.
[0077]
Third Embodiment The CMUT array according to the third embodiment is characterized in that a
sidewall is provided on the outer peripheral portion of the lower electrode in order to reduce a
04-05-2019
24
step due to the lower electrode.
[0078]
FIG. 16 is a top view of the CMUT array according to the present embodiment.
Reference numeral 1703 is a lower electrode, 1705 is a cavity, 1707 is an upper electrode, 1708
is a wire connecting the upper electrode 1707, and 1710 is a wet etching hole for forming the
cavity 1705.
That is, the wet etching hole 1710 is connected to the hollow portion 1705. Reference numeral
1601 denotes a pad opening to a pad provided in the same layer as the lower electrode 1703 to
supply power to the upper electrode 1707, and 1602 denotes a plug for connecting the pad and
the wiring 1708. That is, the pad is connected to the wiring 1708 connecting the upper electrode
1707 through the plug 1602. Reference numeral 1603 denotes a pad opening for supplying
power to the lower electrode 1703. Sidewalls 1712 are formed on the outer peripheral portion of
the lower electrode 1703. An insulating film is formed between the upper electrode 1707 and
the wiring 1708 and the lower electrode 1703 so as to cover the cavity 1705, the sidewall 1712
and the lower electrode 1703. However, the insulating film is formed between the cavity 1705,
the lower electrode 1703, and the sidewall 1712. Not shown to show.
[0079]
FIG. 17 (a) shows a cross section in the A-A 'direction of FIG. 16, and FIG. 17 (b) shows a cross
section in the B-B' direction of FIG. As shown in FIGS. 17A and 17B, the lower electrode 1703 is
formed on the insulating film 1702 formed on the semiconductor substrate 1701. Side walls
1712 made of an insulating film are formed on the side walls of the lower electrode 1703. A
cavity 1705 is formed on the lower electrode 1703 and the side wall 1712 with an insulating
film 1704 interposed therebetween.
[0080]
An insulating film 1706 is formed so as to surround the hollow portion 1705, and a wire 1708
connecting the upper electrode 1707 and the upper electrode is formed on the insulating film
1706.
04-05-2019
25
[0081]
An insulating film 1709 and an insulating film 1711 are formed over the upper electrode 1707
and the wiring 1708.
In addition, wet etching holes 1710 which penetrate these films are formed in the insulating film
1706 and the insulating film 1709. The wet etching hole 1710 is formed to form a cavity 1705,
and is filled with an insulating film 1711 after the cavity 1705 is formed.
[0082]
The feature of the third embodiment is that a sidewall 1712 made of an insulating film is
provided on the outer peripheral portion of the lower electrode 1703 as shown in FIG. 16 and
FIGS. 17 (a) and 17 (b).
[0083]
With such a configuration, the level difference due to the lower electrode 1703 is alleviated, the
step coverage at the level difference portion of the wiring 1708 can be improved, and resistance
increase and disconnection of the wiring can be suppressed.
In particular, if the step by the lower electrode 1703 is 500 nm or more, the step coverage at the
step portion is further reduced. Therefore, when the step by the lower electrode 1703 is 500 nm
or more, the sidewall 1712 is provided on the outer peripheral portion of the lower electrode
1703. Is valid.
[0084]
Further, when the upper electrode 1707 and the wiring 1708 are patterned, the local level
difference due to the lower electrode 1703 is alleviated, so the amount of over-etching for
removing the wiring material in the level difference portion can be reduced. That is, when the
over-etching amount is large, the insulating film 1706 in the lower layer of the upper electrode
04-05-2019
26
1707 is scraped to change the membrane film thickness of the CMUT cell, which causes the
fluctuation of the operating characteristics. However, in the structure shown in the third
embodiment, the local step difference is mitigated by forming the side wall on the outer
periphery of the lower electrode, so that the amount of over-etching can be reduced. The amount
of scraping can be reduced and the operation stability can be improved.
[0085]
Furthermore, the insulating films 1704 and 1706 which insulate the lower electrode 1703 and
the upper electrode 1707 can also reduce the decrease in film thickness at the step portion of
the lower electrode 1703 by forming the sidewalls 1712 and suppress the decrease in insulation
resistance. And improve device reliability.
[0086]
Furthermore, as described in the first embodiment, if the wiring width of only the wiring
overlapping with the sidewall 1712 is increased, the resistance increase and the disconnection of
the wiring can be further suppressed.
[0087]
The method of manufacturing a CMUT array according to the third embodiment is substantially
the same as that of the first embodiment except that a sidewall 1712 is formed on the outer
peripheral portion of the lower electrode 1703.
[0088]
18 to 20 show a manufacturing method from formation of the lower electrode to formation of a
sidewall.
(A) of each figure shows the A-A 'cross section of FIG. 16, (b) shows the B-B' cross section of FIG.
[0089]
First, as shown in FIGS. 18A and 18B, an insulating film 1702 made of a silicon oxide film is
formed on a semiconductor substrate 1701 by plasma CVD, and then a titanium nitride film, an
04-05-2019
27
aluminum alloy film, and titanium nitride are formed by sputtering. The lower electrode 1703 is
formed by stacking the films at 100 nm, 600 nm, and 100 nm, respectively, and patterning the
film by photolithography and dry etching.
An insulating film 1901 of silicon oxide film is deposited 600 nm thick on the lower electrode
1703 by plasma CVD.
(FIG. 19 (a) (b)).
[0090]
Next, the insulating film 1901 of silicon oxide film is anisotropically etched by dry etching until
the surface of the lower electrode 1703 is exposed, whereby the sidewall 1712 of silicon oxide
film can be formed on the outer peripheral portion of the lower electrode 1703. . (FIG. 20 (a) (b)).
The subsequent steps are the same as in the first embodiment.
[0091]
Although the CMUT array shown in FIG. 16 has a configuration in which CMUT cells in two rows
and one column are arranged at the cross point of the lower electrode 1703 and the upper
electrode 1707, as shown in the first embodiment, many rows are provided. Even in the case
where a large number of rows of CMUT cells are arranged, the same effect can be obtained by
providing a sidewall on the outer peripheral portion of the lower electrode.
[0092]
Further, in FIG. 16, the CMUT cell has a hexagonal shape, but the shape is not limited to this, and
may have, for example, a circular shape.
[0093]
Moreover, the material which comprises the CMUT cell shown as this Embodiment 3 shows one
of the combination.
04-05-2019
28
The material of the sacrificial layer also needs to ensure the wet etching selectivity with the
material surrounding the sacrificial layer.
Therefore, in addition to the polycrystalline silicon film, an SOG film or a metal film may be used.
[0094]
Fourth Embodiment The CMUT array according to the fourth embodiment is characterized in that
flattening is performed on the upper surface of the lower electrode in order to reduce a step due
to the lower electrode.
[0095]
FIG. 21 shows a top view of the CMUT array in the fourth embodiment.
Reference numeral 2203 denotes a lower electrode, 2206 denotes a hollow portion, 2208
denotes an upper electrode, 2209 denotes a wire connecting the upper electrode 2208, and
2211 denotes a wet etching hole for forming the hollow portion 2206. That is, the wet etching
hole 2211 is connected to the hollow portion 2206.
[0096]
Reference numeral 2101 denotes a pad opening to a pad provided in the same layer as the lower
electrode 2203 in order to supply power to the upper electrode 2208, and reference numeral
2102 denotes a plug for connecting the pad and the wiring 2209. That is, the pad is connected to
the wire 2209 connecting the upper electrode 2208 through the plug 2102.
[0097]
Reference numeral 2103 denotes a pad opening for supplying power to the lower electrode
2203. An insulating film 2204 is embedded in the gap of the lower electrode 2203. An insulating
film is formed so as to cover the cavity 2206 and the lower electrode 2203 between the upper
electrode 2208 and the wiring 2209 and the lower electrode 2203, but to show the cavity 2206,
04-05-2019
29
the lower electrode 2203, and the insulating film 2204. Not shown.
[0098]
22A shows a cross section in the A-A 'direction of FIG. 21, and FIG. 22B shows a cross section in
the B-B' direction of FIG.
[0099]
As shown in FIGS. 22A and 22B, the lower electrode 2203 is formed on the insulating film 2202
formed on the semiconductor substrate 2201.
An insulating film 2204 is embedded between the lower electrodes 2203 and planarized so that
the upper surface of the lower electrode 2203 and the upper surface of the insulating film 2204
coincide with each other. An insulating film 2205 is formed on the lower electrode 2203 and the
insulating film 2204, and a cavity 2206 is formed on the lower electrode 2203 via the insulating
film 2205. An insulating film 2207 is formed so as to surround the hollow portion 2206, and an
upper electrode 2208 and a wire 2209 connecting the upper electrode are formed on the
insulating film 2207. An insulating film 2210 and an insulating film 2212 are formed over the
upper electrode 2208 and the wiring 2209. In the insulating film 2210 and the insulating film
2207, wet etching holes 2211 penetrating these films are formed. The wet etching hole 2211 is
formed to form a cavity 2206, and is filled with an insulating film 2212 after the cavity 2206 is
formed.
[0100]
A feature of the fourth embodiment is that the insulating film 2204 is embedded between the
lower electrodes 2203 as shown in FIG. 21, FIG. 22 (a) and FIG. 22 (b) to perform planarization.
[0101]
With such a configuration, the step due to the lower electrode 2203 is eliminated, the coverage is
not lowered at the step portion of the wiring 2209 connecting the upper electrode 2208, and the
resistance increase and the disconnection of the wiring can be suppressed.
04-05-2019
30
In particular, if the step by the lower electrode 2203 is 500 nm or more, the step coverage at the
step portion is further reduced. Therefore, when the step by the lower electrode 2203 is 500 nm
or more, the insulating film 2204 is embedded between the lower electrode 2203 to be flat. Is
effective.
[0102]
In addition, when the upper electrode 2208 is patterned, the amount of over-etching for etching
the wiring material can be reduced because there is no stepped portion due to the lower
electrode 2203. That is, when the amount of over-etching is large, the insulating film 2207 in the
lower layer of the upper electrode 2208 is scraped to change the thickness of the membrane of
the CMUT cell, which causes the variation of the operating characteristics. However, in the
structure shown in the fourth embodiment, since the gap between the lower electrodes is filled
with the insulating film and flattened, the level difference is eliminated, and the amount of overetching can be reduced. That is, the amount of scraping of the insulating film 2207 can be
reduced, and the operation stability can be improved.
[0103]
Furthermore, since the insulating films 2205 and 2207 which insulate the lower electrode 2203
and the upper electrode 2208 also have no step due to the lower electrode 2203, the insulation
resistance is not lowered and the reliability of the device can be improved.
[0104]
The method of manufacturing a CMUT array according to the fourth embodiment is substantially
the same as that of the first embodiment, except that the insulating film is embedded between
the lower electrodes and planarized.
[0105]
FIGS. 23 and 24 show from the formation of the insulating film filling the space between the
lower electrodes to the flattening of the insulating film.
(A) of each figure shows the A-A 'cross section of FIG. 21, (b) shows the B-B' cross section of FIG.
04-05-2019
31
[0106]
First, as shown in FIGS. 23A and 23B, an insulating film 2202 of silicon oxide film is formed on a
semiconductor substrate 2201 by plasma CVD method, and then titanium nitride film, aluminum
alloy film and nitride film are nitrided by sputtering method. A lower electrode 2203 is formed
by laminating a titanium film to 100 nm, 600 nm, and 100 nm and then patterning the film by
photolithography and dry etching.
An insulating film 2301 of silicon oxide film is deposited to 1400 nm on the lower electrode
2203 by plasma CVD.
[0107]
Next, the insulating film 2301 made of a silicon oxide film is planarized by CMP (Chemical
Mechanical Polishing) until the surface of the lower electrode 2203 is exposed, whereby the
silicon oxide film embedded and planarized between the lower electrodes is formed. The
insulating film 2204 can be formed by (FIG. 24 (a) (b)). The subsequent steps are the same as in
the first embodiment.
[0108]
In the fourth embodiment, the insulating film 2301 made of a silicon oxide film is planarized by
CMP until the surface of the lower electrode 2203 is exposed. However, the planarizing is
performed by CMP until just before the surface of the lower electrode 2203 is exposed.
Thereafter, the same shape can be obtained by etching the insulating film 2301 made of a silicon
oxide film until the surface of the lower electrode 2203 is exposed by dry etching.
[0109]
In order to precisely planarize the silicon oxide film, as shown in FIGS. 25 to 28, a stop film for
the planarization process by the CMP technique may be inserted.
(A) of each figure shows the A-A 'cross section of FIG. 21, (b) shows the B-B' cross section of FIG.
04-05-2019
32
As shown in FIGS. 25A and 25B, after the lower electrode 2203 is formed, an insulating film
2501 of silicon nitride is formed to a thickness of 200 nm by plasma CVD as a stop film for the
planarization CMP process. Thereafter, an insulating film 2601 made of a silicon oxide film is
deposited on the insulating film 2501 made of a silicon nitride film to a thickness of 1400 nm by
plasma CVD. (FIG. 26 (a), (b)). Subsequently, the insulating film 2601 made of a silicon oxide film
is planarized by CMP until the upper surface of the insulating film 2501 made of a silicon nitride
film is exposed. (FIG. 27 (a), (b)). At this time, since the polishing rate ratio in CMP of the silicon
oxide film and the silicon nitride film is 2-3, it is possible to controlly stop the polishing on the
upper surface of the insulating film 2501 of the silicon nitride film in a controlled manner.
Thereafter, the insulating film 2601 made of a silicon oxide film and the insulating film 2501
made of a silicon nitride film are etched at a constant speed by dry etching to expose the surface
of the lower electrode 2203 and form a planarized structure between the lower electrodes. be
able to. (FIG. 28 (a), (b)).
[0110]
Furthermore, in the fourth embodiment, the insulating film 2204 for filling the space between
the lower electrodes 2203 is formed by plasma CVD, but an SOG film may be embedded by a
coating method. In that case, after the SOG film is embedded, dry back is performed by dry
etching until the surface of the lower electrode is exposed, whereby a planarized structure similar
to that shown in FIGS. 24 and 28 can be obtained.
[0111]
Further, even if the lower electrode is formed by the embedded wiring by the damascene method,
it is possible to obtain a similar planarized structure on the upper surface of the lower electrode.
In that case, it can be realized by forming a groove shape in the insulating film in advance by
etching, embedding a material to be a lower electrode in the groove, and polishing and removing
an excess lower electrode material protruding from the groove.
[0112]
Although the CMUT array shown in FIG. 21 has a configuration in which CMUT cells in two rows
and one column are arranged at the cross point of the lower electrode 2203 and the upper
electrode 2208, as shown in the first embodiment, many rows are provided. Even in the case
where a large number of rows of CMUT cells are arranged, similar effects can be obtained by
performing planarization on the upper surface of the lower electrode.
04-05-2019
33
[0113]
Further, in FIG. 21, the CMUT cell has a hexagonal shape, but the shape is not limited to this, and
may have, for example, a circular shape.
[0114]
Further, the material constituting the CMUT cell shown as the fourth embodiment shows one of
the combinations.
The material of the sacrificial layer also needs to ensure the wet etching selectivity with the
material surrounding the sacrificial layer.
Therefore, in addition to the polycrystalline silicon film, an SOG film or a metal film may be used.
[0115]
Fifth Embodiment In the CMUT array according to the fifth embodiment, the upper surface of the
lower electrode is planarized in order to reduce the level difference due to the lower electrode,
and the dummy pattern for planarization is formed in the same layer as the lower electrode. It is
characterized by forming.
[0116]
FIG. 29 shows a top view of the CMUT array of the fifth embodiment.
3003 is a lower electrode, 3007 is a cavity, 3009 is an upper electrode, 3010 is a wire
connecting the upper electrode 3009, and 3012 is a wet etching hole for forming the cavity
3007. That is, the wet etching hole 3012 is connected to the hollow portion 3007.
[0117]
04-05-2019
34
Reference numeral 2901 denotes a pad opening to a pad provided in the same layer as the lower
electrode 3003 in order to supply power to the upper electrode 3009, and reference numeral
2902 denotes a plug for connecting the pad and the wiring 3010. That is, the pad is connected to
the wiring 3010 connecting the upper electrode 3009 through the plug 2902. Reference
numeral 2903 denotes a pad opening for supplying power to the lower electrode 3003. A
dummy pattern 3004 for planarization is formed between the lower electrodes 3003. An
insulating film 3005 is embedded in the gap between the dummy pattern 3004 and the lower
electrode 3003.
[0118]
An insulating film is formed between the upper electrode 3009 and the wiring 3010 and the
lower electrode 3003 so as to cover the cavity 3007, the dummy pattern 3004, the insulating
film 3005 and the lower electrode 3003. The cavity 3007, the lower electrode 3003, The dummy
pattern 3004 and the insulating film 3005 are not shown to show them.
[0119]
FIG. 30 shows a cross section of a CMUT array according to the fifth embodiment.
FIG. 30 (a) shows a cross section in the A-A 'direction of FIG. 29, and FIG. 30 (b) shows a cross
section in the B-B' direction of FIG.
[0120]
As shown in FIGS. 30A and 30B, the lower electrode 3003 is formed on the insulating film 3002
formed on the semiconductor substrate 3001. A dummy pattern 3004 for planarization is also
formed simultaneously with the lower electrode 3003. That is, the lower electrode 3003 and the
dummy pattern 3004 are formed at the same height.
[0121]
An insulating film 3005 is embedded between the lower electrode 3003 and the dummy pattern
04-05-2019
35
3004, and is planarized so that the upper surfaces of the lower electrode 3003 and the dummy
pattern 3004 and the upper surface of the insulating film 3005 coincide with each other. The
insulating film 3005 is provided to electrically insulate the lower electrode 3003 and the dummy
pattern 3004.
[0122]
An insulating film 3006 is formed on the lower electrode 3003, the dummy pattern 3004, and
the insulating film 3005, and a cavity 3007 is formed on the lower electrode 3003 with the
insulating film 3006 interposed therebetween. An insulating film 3008 is formed so as to
surround the hollow portion 3007, and a wire 3010 connecting the upper electrode 3009 and
the upper electrode is formed on the insulating film 3008. An insulating film 3011 and an
insulating film 3013 are formed over the upper electrode 3009 and the wiring 3010. In the
insulating film 3011 and the insulating film 3008, wet etching holes 3012 penetrating these
films are formed. The wet etching hole 3012 is formed to form a cavity 3007, and is filled with
an insulating film 3013 after the cavity 3007 is formed.
[0123]
The feature of the fifth embodiment is that a dummy pattern 3004 is provided between the lower
electrode 3003 as shown in FIGS. 29, 30 (a) and 30 (b), and an insulating film is formed in the
gap between the lower electrode 3003 and the dummy pattern 3004. It is in the point which
embedded by 3005 and flattened.
[0124]
With such a configuration, the flatness in the CMP process for flattening the steps by the lower
electrode 3003 can be further improved.
That is, if the dummy pattern 3004 is not present, there is a possibility that the amount of
depression of the insulating film 3005 in the region where the lower electrode 3003 does not
exist in the base is large due to a phenomenon called dishing at the CMP polishing of the
insulating film 3005. However, in the structure shown in the fifth embodiment, the dummy
pattern 3004 improves the flatness of the insulating film 3005 by CMP, and can further reduce
the step due to the lower electrode 3003. Disconnection can be suppressed. That is, by forming
the dummy pattern 3004 made of the same material as the lower electrode 3003 between the
04-05-2019
36
lower electrodes 3003, it is possible to prevent dishing when the dummy patterns 3004 are not
formed. In particular, if the step by the lower electrode 3003 is 500 nm or more, the step
coverage at the step portion is further reduced. Therefore, when the step by the lower electrode
3003 is 500 nm or more, the dummy pattern 3004 and the insulating film 3005 are interposed
between the lower electrode 3003. Embedding and flattening is effective.
[0125]
In addition, the amount of overetching when patterning the upper electrode 3009 can be
reduced, the amount of scraping of the insulating film 3008 can be reduced, and the operation
stability can be improved.
[0126]
Furthermore, since the insulating films 3006 and 3008 which insulate the lower electrode 3003
and the upper electrode 3009 also have no step due to the lower electrode 3003, the insulation
resistance is not lowered and the reliability of the device can be improved.
[0127]
The method of manufacturing a CMUT array according to the fifth embodiment is substantially
the same as that of the fourth embodiment except that a dummy pattern is formed in the same
layer as the lower electrode.
[0128]
31 to 33 show a method of forming a lower electrode and a dummy pattern for planarization,
and a manufacturing method from formation of an insulating film filling the space between the
lower electrodes to planarization of the insulating film.
(A) of each figure shows a cross section in the A-A 'direction of FIG. 29, and (b) shows a cross
section in the B-B' direction of FIG.
[0129]
First, as shown in FIGS. 31A and 31B, an insulating film 3002 made of a silicon oxide film is
04-05-2019
37
formed on a semiconductor substrate 3001 by plasma CVD.
Thereafter, a titanium nitride film, an aluminum alloy film, and a titanium nitride film are
respectively stacked by 100 nm, 600 nm, and 100 nm by sputtering, and then patterned by
photolithography and dry etching to form the lower electrode 3003.
At this time, a dummy pattern 3004 for planarization is simultaneously formed. An insulating
film 3005 of silicon oxide film is deposited on the lower electrode 3003 and the dummy pattern
3004 by plasma CVD to a thickness of 1400 nm. (FIG. 32 (a), (b)).
[0130]
Next, the insulating film 3005 made of a silicon oxide film is planarized by CMP until the
surfaces of the lower electrode 3003 and the dummy pattern 3004 are exposed, so that the
silicon embedded between the lower electrode and the dummy pattern is planarized. The
structure of the insulating film 3005 can be formed of an oxide film. (FIG. 33 (a) (b)). The
subsequent steps are the same as in the fourth embodiment.
[0131]
In the fifth embodiment, the silicon oxide film is planarized by the CMP technique until the
surfaces of the lower electrode 3003 and the dummy pattern 3004 are exposed. However, the
CMP technique is performed until just before the surfaces of the lower electrode 3003 and the
dummy pattern 3004 are exposed. The same shape is obtained even if the silicon oxide film is
etched until the surfaces of the lower electrode 3003 and the dummy pattern 3004 are exposed
by dry etching technology after flattening.
[0132]
Further, in order to accurately planarize the silicon oxide film, a stop film for the planarization
process by CMP may be inserted in the upper layer of the lower electrode 3003 and the dummy
pattern 3004.
[0133]
04-05-2019
38
Furthermore, in the fifth embodiment, the insulating film 3005 filling the gap between the lower
electrode 3003 and the dummy pattern 3004 is formed by plasma CVD, but an SOG film may be
embedded by a coating method.
In that case, the gap between the lower electrode 3003 and the dummy pattern 3004 is filled by
applying the SOG film, and then etch back is performed until the surfaces of the lower electrode
3003 and the dummy pattern 3004 are exposed by dry etching. The same planarized structure
can be obtained.
[0134]
In addition, even if the lower electrode 3003 is formed by embedded wiring by a damascene
method, a similar planarized structure can be obtained.
In that case, a groove for the lower electrode and a groove for the dummy pattern are previously
formed in the insulating film by etching, the material to be the lower electrode 3003 is
embedded in these grooves, and the excess lower electrode material protruding from the groove
is It can be realized by polishing and removing.
[0135]
Although the CMUT array shown in FIG. 29 has a configuration in which CMUT cells in two rows
and one column are arranged at the cross point of the lower electrode 3003 and the upper
electrode 3009, as shown in the first embodiment, many rows are provided. Even in the case
where a large number of rows of CMUT cells are arranged, similar effects can be obtained by
performing planarization on the upper surface of the lower electrode and forming a dummy
pattern for planarization in the same layer as the lower electrode.
[0136]
Further, in FIG. 29, the CMUT cell has a hexagonal shape, but the shape is not limited to this, and
may have, for example, a circular shape.
[0137]
04-05-2019
39
Further, the material constituting the CMUT cell shown as the fifth embodiment shows one of the
combinations.
The material of the sacrificial layer also needs to ensure the wet etching selectivity with the
material surrounding the sacrificial layer.
Therefore, in addition to the polycrystalline silicon film, an SOG film or a metal film may be used.
[0138]
Sixth Embodiment The CMUT array according to the sixth embodiment is characterized in that
flattening is performed on the hollow portion in order to reduce a step due to the lower electrode
and the hollow portion.
[0139]
The top view of the CMUT array of the sixth embodiment is the same as that of FIG. 1 in the
arrangement of the electrodes and hollow portions, and therefore, the cross section of the CMUT
array in the sixth embodiment is shown in FIG.
34 (a) shows an A-A 'cross section of FIG. 1, and FIG. 34 (b) shows a B-B' cross section of FIG.
[0140]
As shown in FIGS. 34A and 34B, the lower electrode 203 is formed on the insulating film 202
formed on the semiconductor substrate 201. A cavity 205 is formed on the lower electrode 203
via the insulating film 204. An insulating film 3401 is formed so as to cover the insulating film
204 and the hollow portion 205, and the insulating film 3401 is planarized so as to have the
same height as the top surface of the hollow portion.
[0141]
04-05-2019
40
An insulating film 206 is formed so as to cover the cavity portion 205 and the insulating film
3401, and a wiring 208 connecting the upper electrode 207 and the upper electrode is formed
on the insulating film 206. An insulating film 209 and an insulating film 211 are formed over the
upper electrode 207 and the wiring 208. In the insulating film 209 and the insulating film 206,
wet etching holes 210 penetrating these films are formed. The wet etching holes 210 are formed
to form the hollow portion 205, and are filled with the insulating film 211 after the hollow
portion 205 is formed.
[0142]
The feature of the sixth embodiment resides in that the insulating film 3401 is planarized on the
upper surface of the hollow portion 205 as shown in FIGS. 34 (a) and 34 (b).
[0143]
With such a configuration, the step due to the lower electrode 203 and the step due to the
hollow portion 205 can be simultaneously relieved, and the wire 208 connecting the upper
electrode is not affected by the step, and the resistance of the wire rises. And disconnection can
be suppressed.
[0144]
In addition, when the upper electrode 207 is patterned, the amount of overetching for etching
the wiring material can be reduced because there is no step.
That is, when the over-etching amount is large, the insulating film 206 in the lower layer of the
upper electrode 207 is scraped to change the membrane film thickness of the CMUT cell, which
causes the fluctuation of the operation characteristics. In the structure, the amount of scraping of
the insulating film 206 can be reduced, so that the operation stability can be improved.
[0145]
Further, as shown in FIG. 34A, since the wiring 208 is disposed on the planarized insulating film
206, the insulation resistance with the lower electrode is not reduced, and the reliability of the
device can be improved.
[0146]
04-05-2019
41
The method of manufacturing a CMUT array according to the sixth embodiment is substantially
the same as that of the first embodiment except that planarization is performed on the upper
surface of the cavity.
[0147]
FIG. 35 to FIG. 37 show formation of a sacrificial layer, subsequent filling with an insulating film,
and planarization of the insulating film.
(A) of each figure corresponds to the cross section in the A-A 'direction of FIG. 1, and (b)
corresponds to the cross section in the B-B' direction of FIG.
[0148]
First, as shown in FIGS. 35A and 35B, an insulating film 202 is formed of a silicon oxide film on a
semiconductor substrate 201 by plasma CVD, and then a titanium nitride film, an aluminum alloy
film, and titanium nitride are formed by sputtering. The lower electrode 203 is formed by
depositing the film to 100 nm, 600 nm, and 100 nm, and then patterning the film by
photolithography and dry etching.
An insulating film 204 of silicon oxide film is deposited to 100 nm on the lower electrode 203 by
plasma CVD.
Next, a polycrystalline silicon film is deposited to 200 nm on the upper surface of the insulating
film 204 of silicon oxide film by plasma CVD. Then, the polycrystalline silicon film is left by
photolithography and dry etching. The remaining portion becomes the sacrificial layer 3501 and
becomes the hollow portion 205 of FIG. 34 in the subsequent process.
[0149]
Next, an insulating film 3401 made of a silicon oxide film is deposited to a thickness of 1,400 nm
by plasma CVD so as to cover the sacrificial layer 3501 and the insulating film 204 made of a
04-05-2019
42
silicon oxide film. (FIG. 36 (a), (b)).
[0150]
Thereafter, the insulating film 3401 made of a silicon oxide film is polished by CMP until the top
surface of the sacrificial layer 3501 is exposed, whereby a planarized structure on the top
surface of the sacrificial layer can be obtained. (FIG. 37 (a), (b)). The subsequent steps are the
same as in the first embodiment.
[0151]
In the sixth embodiment, the insulating film 3401 made of a silicon oxide film is planarized by
the CMP technique until the upper surface of the sacrificial layer 3501 is exposed. However, the
planarizing is performed by the CMP technique until just before the upper surface of the
sacrificial layer 3501 is exposed. Then, the same structure can be obtained by etching the
insulating film 3401 made of a silicon oxide film until the upper surface of the sacrificial layer
3501 is exposed by dry etching.
[0152]
Further, in order to accurately planarize the insulating film 3401 using a silicon oxide film, a stop
film for the planarization process using CMP may be inserted in the upper layer of the sacrificial
layer 3501 and the insulating film 204.
In that case, after stopping the polishing of the insulating film 3401 accurately with the
planarization process stop film, the same procedure is performed by etching the stopping film
and the insulating film 3401 at the same speed by dry etching until the upper surface of the
sacrificial layer 3501 is exposed. A flattened structure can be obtained.
[0153]
Furthermore, in the sixth embodiment, the insulating film 3401 to be planarized is formed by
plasma CVD, but the SOG film may be embedded by coating. In that case, after the SOG film is
applied, etch back is performed by dry etching until the upper surface of the sacrificial layer is
04-05-2019
43
exposed, whereby a planarized structure similar to FIG.
[0154]
Although the CMUT array shown in FIG. 1 has a configuration in which CMUT cells in two rows
and one column are disposed at the cross point of the lower electrode 203 and the upper
electrode 207, as shown in the first embodiment, many rows are provided. Even in the case
where a large number of rows of CMUT cells are arranged, similar effects can be obtained by
performing planarization on the cavity.
[0155]
Moreover, in FIG. 1, although the CMUT cell is carrying out the shape of a hexagon, a shape is
not restricted to this, For example, you may have circular shape.
[0156]
Further, the material constituting the CMUT cell shown as the sixth embodiment represents one
of the combinations.
The material of the sacrificial layer also needs to ensure the wet etching selectivity with the
material surrounding the sacrificial layer.
Therefore, in addition to the polycrystalline silicon film, an SOG film or a metal film may be used.
[0157]
Seventh Embodiment A CMUT array according to a seventh embodiment of the present invention
is characterized in that a dummy pattern for planarization is formed in the same layer as the
lower electrode in order to reduce a step due to the lower electrode and the hollow, and To
perform the planarization.
[0158]
A top view of the CMUT array of the seventh embodiment is shown in FIG.
04-05-2019
44
[0159]
3903 is a lower electrode, 3906 is a cavity, 3909 is an upper electrode, 3910 is a wire
connecting the upper electrode 3909, and 3912 is a wet etching hole for forming the cavity
3906.
That is, the wet etching hole 3912 is connected to the hollow portion 3906.
[0160]
Reference numeral 3801 denotes a pad opening to a pad provided in the same layer as the lower
electrode 3903 in order to supply power to the upper electrode 3909, and 3802 denotes a plug
for connecting the pad and the wiring 3910.
That is, the pad is connected to the wiring 3910 connecting the upper electrode 3909 through
the plug 3802. Reference numeral 3803 denotes a pad opening for supplying power to the lower
electrode 3903. A dummy pattern 3904 for planarization is formed between the lower electrodes
3903. An insulating film is formed between the upper electrode 3909 and the lower electrode
3903 so as to cover the cavity 3906, the dummy pattern 3904 and the lower electrode 3903.
However, in order to show the cavity 3906, the lower electrode 3903, and the dummy pattern
3904 Not shown.
[0161]
FIG. 39 shows a cross section of a CMUT array according to the seventh embodiment. 39 (a)
shows an A-A 'cross section of FIG. 38, and FIG. 39 (b) shows a B-B' cross section of FIG.
[0162]
As shown in FIGS. 39A and 39B, the lower electrode 3903 is formed on the insulating film 3902
formed on the semiconductor substrate 3901. A dummy pattern 3904 for planarization is also
formed simultaneously with the lower electrode 3903. A cavity 3906 is formed on the lower
04-05-2019
45
electrode 3903 with an insulating film 3905 interposed therebetween. An insulating film 3907 is
formed to cover the insulating film 3905 and the cavity 3906, and the insulating film 3907 is
planarized so as to have the same height as the upper surface of the cavity. An insulating film
3908 is formed so as to cover the cavity 3906 and the insulating film 3907, and a wire 3910
connecting the upper electrode 3909 and the upper electrode 3909 is formed on the insulating
film 3908. An insulating film 3911 and an insulating film 3913 are formed on the upper layer of
the upper electrode 3909. In addition, wet etching holes 3912 which penetrate these films are
formed in the insulating film 3908 and the insulating film 3911. The wet etching holes 3912 are
formed to form a cavity 3906, and are embedded with an insulating film 3913 after the cavity
3906 is formed.
[0163]
The feature of the seventh embodiment is that a dummy pattern 3904 is provided between the
lower electrode 3903 as shown in FIG. 38 and FIGS. 39A and 39B, and a gap between the lower
electrode 3903 and the dummy pattern 3904 An insulating film 3907 is formed over the cavity
3906 and the insulating film 3905, and the insulating film 3907 is planarized on the upper
surface of the cavity 3906.
[0164]
With such a configuration, the flatness in the CMP process for flattening the steps due to the
lower electrode 3903 can be further improved.
[0165]
That is, if the dummy pattern 3904 is not present, the amount of depression of the insulating
film 3907 in the region where the lower electrode 3903 does not exist in the base is increased
during the CMP process of the insulating film 3907 due to a phenomenon called dishing.
However, in the structure shown in the seventh embodiment, the flatness of the insulating film
3907 by CMP can be improved by the dummy pattern 3904, and the step due to the lower
electrode 3903 can be further alleviated.
[0166]
Therefore, as compared with the case where the dummy pattern 3904 is not provided, the wire
3910 connecting the upper electrode 3909 can be further prevented from the resistance
04-05-2019
46
increase and the disconnection of the wire without the influence of the step.
[0167]
In addition, when the upper electrode 3910 is patterned, the amount of over-etching for etching
the wiring material can be further reduced because there is no step.
Furthermore, as shown in FIG. 39A, since the wiring 3910 is disposed on the planarized
insulating film 3908, the insulation resistance with the lower electrode 3903 is not reduced, and
the reliability of the device can be improved. .
[0168]
The method of manufacturing a CMUT array according to the seventh embodiment is
substantially the same as that of the sixth embodiment except that a dummy pattern for
planarization is formed in the same layer as the lower electrode.
[0169]
In the same manner as in the sixth embodiment, the method of planarization may be
planarization by CMP process after forming the insulating film by plasma CVD method, or
planarization by combination of CMP process and dry etching.
Furthermore, after a stop film for the planarization process is inserted in the upper layer of the
cavity and polishing of the insulating film is accurately stopped at the planarization process stop
film, the stop film is dry etched until the upper surface of the sacrificial layer is exposed. The
same planarized structure can be obtained by etching the insulating film at a constant rate.
[0170]
Alternatively, the same planarized structure can be obtained by embedding the SOG film by a
coating method without using a CMP process and performing etch back until the upper surface
of the sacrificial layer is exposed by dry etching.
04-05-2019
47
[0171]
In addition, in order to obtain a planarized structure on the upper surface of the cavity 3906, the
same structure can be obtained by forming a sacrificial layer which is the base of the cavity 3906
by a damascene method.
In that case, a groove for a sacrificial layer may be formed in advance in the insulating film by
etching, the material serving as the sacrificial layer may be embedded in the groove, and the
extra material protruding from the groove may be polished.
[0172]
Although the CMUT array shown in FIG. 38 has a configuration in which CMUT cells in two rows
and one column are disposed at the cross point of the lower electrode 3903 and the upper
electrode 3909, as shown in the first embodiment, many rows are provided. Even in the case
where a large number of rows of CMUT cells are arranged, similar effects can be obtained by
forming a dummy pattern for planarization in the same layer as the lower electrode and
performing planarization on the cavity.
[0173]
Further, in FIG. 38, the CMUT cell has a hexagonal shape, but the shape is not limited to this, and
may have, for example, a circular shape.
[0174]
The material constituting the CMUT cell shown as the seventh embodiment represents one of the
combinations.
The material of the sacrificial layer also needs to ensure the wet etching selectivity with the
material surrounding the sacrificial layer.
Therefore, in addition to the polycrystalline silicon film, an SOG film or a metal film may be used.
04-05-2019
48
[0175]
Eighth Embodiment In the CMUT array according to the eighth embodiment, a dummy pattern
for planarization is formed in the same layer as the lower electrode and the cavity in order to
reduce a step due to the lower electrode and the cavity. It is characterized in that flattening is
performed on the hollow portion.
[0176]
FIG. 40 shows a top view of the CMUT array of the eighth embodiment.
4103 is a lower electrode, 4106 is a cavity, 4110 is an upper electrode, 4111 is a wire
connecting the upper electrode 4110, and 4113 is a wet etching hole for forming the cavity
4106.
That is, the wet etching hole 4113 is connected to the hollow portion 4106. Reference numeral
4001 denotes a pad opening to a pad provided in the same layer as the lower electrode 4103 in
order to supply power to the upper electrode 4110, and reference numeral 4002 denotes a plug
for connecting the pad and the wiring 4111. That is, the pad is connected to the wiring 4111
connecting the upper electrode 4110 through the plug 4002. Reference numeral 4003 denotes a
pad opening for supplying power to the lower electrode 4103. A dummy pattern 4104 for
planarization is formed in the same layer as the lower electrode 4103 between the lower
electrodes 4103. Reference numeral 4107 denotes a dummy pattern formed in the same layer as
the hollow portion.
[0177]
An insulating film is formed between the upper electrode 4110 and the lower electrode 4103 so
as to cover the cavity 4106, the dummy patterns 4104 and 4107, and the lower electrode 4103,
but the cavity 4106, the lower electrode 4103, the dummy patterns 4104 and 4107 Not shown
to show.
[0178]
FIG. 41 shows a cross section of a CMUT array according to the eighth embodiment.
04-05-2019
49
41 (a) shows an A-A 'cross section of FIG. 40, and FIG. 41 (b) shows a B-B' cross section of FIG.
[0179]
As shown in FIGS. 41A and 41B, the lower electrode 4103 is formed on the insulating film 4102
formed on the semiconductor substrate 4101.
[0180]
A dummy pattern 4104 for planarization is also formed simultaneously with the lower electrode
4103.
A cavity 4106 is formed on the lower electrode 4103 with the insulating film 4105 interposed
therebetween. A dummy pattern 4107 for planarization is also formed in the same layer as the
cavity portion. An insulating film 4108 is formed to cover the insulating film 4105, the cavity
4106, and the dummy pattern 4107, and the insulating film 4108 is planarized so as to have the
same height as the upper surface of the cavity. An insulating film 4109 is formed to cover the
cavity 4106, the dummy pattern 4107, and the insulating film 4108, and a wiring 4111
connecting the upper electrode 4110 and the upper electrode is formed on the insulating film
4109. An insulating film 4112 and an insulating film 4114 are formed on the upper layer of the
upper electrode 4110. Further, in the insulating film 4109 and the insulating film 4112, wet
etching holes 4113 penetrating these films are formed. The wet etching hole 4113 is formed to
form a cavity 4106, and is filled with an insulating film 4114 after the cavity 4106 is formed.
[0181]
As shown in FIGS. 40 and 41A and 41B, the eighth embodiment is characterized in that dummy
patterns 4104 and 4107 are provided in the same layer as the lower electrode 4103 and in the
same layer as the cavity. The gap between the electrode 4103 and the dummy pattern 4104 and
the space between the cavity 4106 and the dummy pattern 4107 is filled with the insulating film
4108, and the insulating film 4108 is planarized on the upper surface of the cavity 4106.
[0182]
With such a configuration, the flatness can be further improved in the CMP process for flattening
the steps by the lower electrode 4103 and the cavity 4106.
04-05-2019
50
[0183]
That is, without the dummy patterns 4104 and 4107, a phenomenon called dishing causes an
increase in the amount of depression of the insulating film 4108 in a region where the lower
electrode 4103 or the cavity 4106 does not exist as a base during CMP polishing of the
insulating film 4108. .
However, in the structure shown in the eighth embodiment, the flatness of the insulating film
4108 by CMP can be improved by the dummy patterns 4104 and 4107, and the step due to the
lower electrode 4103 and the cavity 4106 can be further alleviated.
[0184]
Further, when the upper electrode 4110 is patterned, the amount of overetching for etching the
wiring material can be further reduced because there is no step.
Further, as shown in FIG. 41A, since the wiring 4111 is disposed on the planarized insulating film
4109, the insulation resistance with the lower electrode 4103 is not lowered, and the reliability
of the device can be improved.
[0185]
The manufacturing method of the CMUT array in the eighth embodiment is the same as that of
the seventh embodiment except that a dummy pattern for planarization is formed in the same
layer as the hollow portion.
[0186]
Also in the eighth embodiment, as in the case of the seventh embodiment, it is obvious that the
planarization process may be performed only by the CMP technique or a combination of the CMP
technique and the dry etching technique.
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Further, as in the case of the seventh embodiment, the stop film of the CMP process may be
inserted in the upper layer of the sacrificial layer.
[0187]
Furthermore, also in the eighth embodiment, an insulating film to be planarized may be
embedded with an SOG film formed by a coating method. In that case, after the SOG film is
applied, etch back is performed by dry etching until the upper surface of the sacrificial layer is
exposed, whereby a planarized structure similar to that shown in FIG. 41 can be obtained.
[0188]
In addition, in order to obtain a planarized structure on the upper surface of the cavity 4106, the
same structure can be obtained by forming a sacrificial layer which is the base of the cavity 4106
by a damascene method. In that case, a groove for a sacrificial layer is formed in advance in the
insulating film by etching, the material to be the sacrificial layer is embedded in the groove, and
the extra material protruding from the groove is polished.
[0189]
Although the CMUT array shown in FIG. 40 has a configuration in which CMUT cells in two rows
and one column are arranged at the cross point of lower electrode 4103 and upper electrode
4110, as shown in the first embodiment, many rows are provided. Even in the case where a large
number of rows of CMUT cells are disposed, the same effect can be obtained by forming a
dummy pattern for planarization in the same layer as the lower electrode and the cavity and by
performing planarization on the cavity.
[0190]
Further, in FIG. 40, the CMUT cell has a hexagonal shape, but the shape is not limited to this, and
may have, for example, a circular shape.
[0191]
Further, the material constituting the CMUT cell shown as the eighth embodiment shows one of
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the combinations.
The material of the sacrificial layer also needs to ensure the wet etching selectivity with the
material surrounding the sacrificial layer.
Therefore, in addition to the polycrystalline silicon film, an SOG film or a metal film may be used.
[0192]
Ninth Embodiment In the CMUT array according to the ninth embodiment, a dummy pattern for
planarization is formed in the same layer as the lower electrode and the cavity in order to reduce
a step due to the lower electrode and the cavity. Planarization is performed on the lower
electrode and the cavity.
[0193]
FIG. 42 shows a top view of the CMUT array of the ninth embodiment.
4303 is a lower electrode, 4307 is a hollow portion, 4311 is an upper electrode, 4312 is a wire
connecting the upper electrode 4311, and 4314 is a wet etching hole for forming the hollow
portion 4307. That is, the wet etching hole 4314 is connected to the hollow portion 4307.
Reference numeral 4201 denotes a pad opening to a pad provided in the same layer as the lower
electrode 4303 in order to supply power to the upper electrode 4311. Reference numeral 4202
denotes a plug for connecting the pad and the wiring 4312. That is, the pad is connected to the
wiring 4312 connecting the upper electrode 4311 through the plug 4202. Reference numeral
4203 denotes a pad opening for supplying power to the lower electrode 4303. A dummy pattern
4308 is formed in the same layer as the hollow portion. Although a dummy pattern for
planarization is formed between the lower electrodes 4303 in the same layer as the lower
electrode 4303, it is not shown because it is covered by the dummy patterns 4308. An insulating
film is formed between the upper electrode 4311 and the lower electrode 4303 so as to cover
the cavity 4307, the dummy pattern in the same layer as the lower electrode, and the dummy
pattern 4308 and the lower electrode 4303 in the same layer as the cavity. The cavity 4307, the
lower electrode 4303 and the dummy pattern 4308 are not shown in order to show them.
[0194]
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FIG. 43 shows a cross section of a CMUT array according to the ninth embodiment. 43 (a) shows
an A-A 'cross section of FIG. 42, and FIG. 43 (b) shows a B-B' cross section of FIG.
[0195]
As shown in FIGS. 43A and 43B, the lower electrode 4303 of the CMUT is formed on the
insulating film 4302 formed on the semiconductor substrate 4301.
[0196]
A dummy pattern 4304 for planarization is also formed simultaneously with the lower electrode
4303.
An insulating film 4305 is embedded between the lower electrode 4303 and the dummy pattern
4304, and the upper surface of the lower electrode 4303 and the upper surface of the insulating
film 4305 are planarized so that the heights thereof coincide with each other. An insulating film
4306 is formed on the lower electrode 4303, the dummy pattern 4304 and the insulating film
4305, and a cavity 4307 is formed on the lower electrode 4303 via the insulating film 4306.
[0197]
A dummy pattern 4308 for planarization is also formed in the same layer as the hollow portion
4307. An insulating film 4309 is formed to cover the insulating film 4306, the cavity 4307, and
the dummy pattern 4308, and the insulating film 4309 is planarized so as to have the same
height as the upper surface of the cavity. An insulating film 4310 is formed so as to cover the
hollow portion 4307, the dummy pattern 4308, and the insulating film 4309, and a wire 4312
connecting the upper electrode 4311 and the upper electrode is formed on the insulating film
4310. An insulating film 4313 and an insulating film 4315 are formed on the upper layer of the
upper electrode 4311. In the insulating film 4310 and the insulating film 4313, wet etching
holes 4314 penetrating these films are formed. The wet etching hole 4314 is formed to form a
cavity 4307 and is filled with an insulating film 4315 after the cavity 4307 is formed.
[0198]
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The feature of the ninth embodiment resides in that a dummy pattern 4304 is provided in the
same layer as the lower electrode 4303 as shown in FIGS. 42, 43A, and 43B, and a gap between
the lower electrode 4303 and the dummy pattern 4304 is provided. The point is that the
insulating film 4305 is embedded and the insulating film 4305 is planarized on the upper
surface of the lower electrode. Furthermore, a dummy pattern 4308 is provided in the same layer
as the hollow portion 4307, the insulating film 4309 is embedded in the gap between the hollow
portion 4307 and the dummy pattern 4308, and the insulating film 4309 is planarized on the
upper surface of the hollow portion 4307.
[0199]
With such a configuration, since the flattening is performed on the lower electrode 4303, the
dummy pattern 4308 in the same layer as the cavity 4307 can be disposed regardless of the
arrangement of the lower electrode 4303, and the lower electrode Flatness in a process for
leveling steps by 4303 and the hollow portion 4307 can be further improved.
[0200]
That is, when planarization is not performed on the lower electrode 4303, the dummy pattern
4308 in the same layer as the cavity 4307 can be disposed only on the lower electrode 4303 or
the dummy pattern 4304 in the same layer as the lower electrode 4303. .
Therefore, the hollow portion 4307 and a region where the dummy pattern 4308 in the same
layer as the hollow portion 4307 is not disposed is called a dishing phenomenon, and the amount
of depression of the insulating film 4309 is increased at the CMP polishing of the insulating film
4309. However, in the structure shown in the ninth embodiment, as shown in FIGS. 42, 43A, and
43B, the dummy pattern 4308 in the same layer as the cavity 4307 is the same as the lower
electrode 4303 and the lower electrode 4303. Since the dummy pattern 4304 can be disposed
independently of the disposition of the dummy pattern 4304 in the layer, the flatness of the
insulating film embedded in the gap between the cavity 4307 and the dummy pattern 4308 in
the same layer as the cavity 4307 is improved by CMP. The level difference can be further
alleviated.
[0201]
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The method of manufacturing a CMUT array according to the ninth embodiment is the same as
the fifth embodiment in that a dummy pattern is disposed in the same layer as the lower
electrode and planarized. The point that the dummy pattern for planarization is disposed in the
same layer as the hollow portion and planarized is the same as the implementation except that
the dummy pattern is disposed independently of the arrangement of the lower electrode and the
dummy pattern in the same layer as the lower electrode. Are the same as in the eighth
embodiment.
[0202]
Also in the ninth embodiment, it is obvious that the planarization process may be performed only
by the CMP technique or a combination of the CMP technique and the dry etching technique.
Also, a stop film of the CMP process may be inserted in the upper layer of the sacrificial layer.
[0203]
Further, also in the ninth embodiment, an insulating film to be planarized may be embedded with
an SOG film formed by a coating method. In that case, after the SOG film is applied, etch back is
performed by dry etching until the upper surface of the sacrificial layer is exposed, whereby a
planarized structure similar to that shown in FIG. 43 can be obtained.
[0204]
Although the CMUT array shown in FIG. 42 has a configuration in which CMUT cells in two rows
and one column are disposed at the cross point of the lower electrode 4303 and the upper
electrode 4311, as shown in the first embodiment, many rows are provided. Even when a large
number of rows of CMUT cells are arranged, similar effects can be obtained by forming a dummy
pattern for planarization in the same layer as the lower electrode and the cavity, and performing
planarization on the lower electrode and the cavity. Is obtained.
[0205]
Further, in FIG. 42, the CMUT cell has a hexagonal shape, but the shape is not limited to this, and
may have, for example, a circular shape.
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[0206]
The material constituting the CMUT cell shown as the ninth embodiment represents one of the
combinations.
The material of the sacrificial layer also needs to ensure the wet etching selectivity with the
material surrounding the sacrificial layer.
Therefore, in addition to the polycrystalline silicon film, an SOG film or a metal film may be used.
[0207]
As mentioned above, although the invention made by the present inventor was concretely
explained based on an embodiment, the present invention is not limited to the above-mentioned
embodiment, and can be variously changed in the range which does not deviate from the gist.
Needless to say.
[0208]
INDUSTRIAL APPLICABILITY The ultrasonic transducer of the present invention can be widely
used in medical inspection and other organizations that perform inspection using ultrasonic
waves, and in the manufacturing industry that manufactures inspection devices.
Also, the manufacturing method can be widely used in the manufacturing industry for
manufacturing ultrasonic transducers.
[0209]
101, 103, 301, 303, 1401, 1403, 1601, 1603, 2101, 2103, 2901, 2903, 3801, 4003, 4001,
4201, and 2043, pad openings 102, 302, 1402, 1602, 2202, and 9023, respectively. 3802,
4002, 4202 plug 201, 401, 1501, 1701, 2201, 3001, 3011, 4101, 431 semiconductor substrate
202, 204, 206, 209, 211, 402, 404, 406, 410, 413, 1502, 1504, 1506 , 1509, 1511, 1702,
1704, 1706, 1709, 1711, 1901, 2202, 2204, 2205, 2207, 2210, 2212, 2301, 2501, 2601,
3002, 300 , 3006, 3008, 3011, 3013, 3013, 3402, 3902, 3905, 3907, 3908, 3911, 3913,
4102, 4105, 4108, 4109, 4112, 4114, 4302, 4305, 4306, 4309, 4310, 4313, 4315 insulating
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film 203, 403, 1503, 1703, 2203, 3003, 3903, 4103, 4303 lower electrodes 205, 412, 1505,
1705, 2206, 3007, 3906, 4106, hollow portions 207, 407, 1507, 1707, 1707, 2208, 3009,
3909, 4110, 4311 Upper electrodes 208, 408, 409, 1508, 1708, 2209, 3010, 3910, 4111,
4312 Wirings 210, 411, 1510, 1710, 221 , 3012,3912,4113,4314 wet etching holes 405,3501
sacrificial layer 1512 tapered portion 1712 sidewall 3004,3904,4104,4107,4304,4308 dummy
pattern
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