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VLSI Signal Processing
Y. V. Joshi
SGGS Institute of Engineering
and Technology, Nanded
IUCEE Workshop presentation-YVJoshi
Introduction
• Efficient implementation of signal
processing algorithms required for real
time signal processing
• Many ways
– Working at architectural level
– Implementation level
• Using Digital Signal Processors
• Using FPGAs
• Using Full custom design
IUCEE Workshop presentation-YVJoshi
Typical DSP algorithms
• Simple
–
–
–
–
Convolution/Correlation
Transformations- FFT/DCT/Wavelet
Digital filtering
Filter banks
• Complex
– Neuro Computing
– Computer Vision
– Artificial organ development
• etc
IUCEE Workshop presentation-YVJoshi
Applications
• MP3 players
• Mobiles
• Embedded systems (automobiles, aircraft,
satellite etc)
• Robots
• Projection systems
• Biomedical/Life support systems
• Communication systems- Software defined
radios, etc
IUCEE Workshop presentation-YVJoshi
Architectural level
• Techniques of reducing the critical path
– Pipelining and Parallel Processing
– Retiming
– Unfolding
– Folding
• Dependent on optimization in data flow
graphs
IUCEE Workshop presentation-YVJoshi
Implementation levelDS Processors
• Selection of DSP based on application
demand
– Analog Devices DSP
– TI DSP
– Motorala DSP
• Selection of Tools/Hardware platforms
• Development of algorithms on DSP
IUCEE Workshop presentation-YVJoshi
Implementation levelFPGA
• Selection of FPGA based on application
demand
– Xilinx
– Alterra
• Selection of Tools/Hardware platforms
• Development of algorithms for FPGA
IUCEE Workshop presentation-YVJoshi
Implementation levelFull Custom VLSI based
• Selection of EDA tool based on application
demand
– Cadence/Tanner/Laker
• Selection of Design methodology
• Development of layouts (LVS/DRC clean)
• Chip mfg.
IUCEE Workshop presentation-YVJoshi
Resources
• Basic units
– Adder
– Multiplier and
– A delay
• Structures used in Signal processing
–
–
–
–
–
Simple Direct form/Transpose form
Cascade/Parallel
Digital two pair/Lattice
Single multiplier per order structure
Derived structures (low sensitivity to coefficient
quantisation)
IUCEE Workshop presentation-YVJoshi
Example
• A second order notch filter
H (z) 
b 0  b1 z
1
 b2 z
2
a 0  a1 z
1
 a2 z
2
• Using allpass structure
H (z) 
1
2
A2 ( z ) 
1 
A 2 ( z ) with
k 2  k 2 (1  k 1 ) z
1  k 2 (1  k 1 ) z
1
1
 z
2
 k2z
2
IUCEE Workshop presentation-YVJoshi
Example (Contd…)
• With values of
k 1   cos(  0 ) and k 2 
1  tan( B / 2 )
1  tan( B / 2 )
• With  0 being the notch frequency and B
being the rejection bandwidth
• implementation with only two multipliers
with minimum critical path
IUCEE Workshop presentation-YVJoshi
Thanks
Contact : Y. V. Joshi
[email protected]
IUCEE Workshop presentation-YVJoshi
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